9702 C++ Programming Manual: D:/9702/Cpp Directory Reference

9702 C++ Programming Manual
Cpp Directory Reference

Files

file JY9702Core.h
Generated by doxygen 1.9.1


9702 C++ Programming Manual: D:/9702/Cpp/JY9702Core.h File Reference

Classes | Macros | Typedefs | Enumerations | Functions
JY9702Core.h File Reference

Classes

struct | JY9702CoreDeviceInfo
struct | JY9702CoreCalibrationConstant
struct | JY9702CoreCalibrationInfo
struct | JY9702DeviceInfo

Macros

#define | STDCALL
FileName:JY9702Core.h Copyright NOTICE(版权声明) Copyright (c) 2017, JXINST All rights reserved. More...
#define | CCALL
#define | JYDLL_API
#define | STDCALL
FileName:JY9702Core.h Copyright NOTICE(版权声明) Copyright (c) 2017, JXINST All rights reserved. More...
#define | Lmk048xxCheckPllStatusCnt (100)
#define | ErrorCodeOffset (int)(-11000)
#define | JYSuccess (0)
#define | JYFailed (-1)
#define | NoError (0)
无错误
More...
#define | ErrorInvalidParam (ErrorCodeOffset-1)
#define | ErrorOpenDeviceFailed (ErrorCodeOffset-2)
#define | ErrorCardNumberNotExistInDeviceManager (ErrorCodeOffset-3)
#define | ErrorLMK048xxInitFailed (ErrorCodeOffset-4)
#define | ErrorLMK048xxGetLockStatusFailed (ErrorCodeOffset-5)
#define | ErrorLMK048xxNotLocked (ErrorCodeOffset-6)
#define | ErrorTxInitFailed (ErrorCodeOffset-7)
#define | ErrorPointerNotNull (ErrorCodeOffset-8)
#define | ErrorCardNotOpened (ErrorCodeOffset-9)
#define | ErrorChannelParam (ErrorCodeOffset-10)
#define | ErrorGenerationModeParam (ErrorCodeOffset-11)
#define | ErrorSamplesParam (ErrorCodeOffset-12)
#define | ErrorClockSource (ErrorCodeOffset-13)
#define | ExternalClockFrequencyParam (ErrorCodeOffset-14)
#define | ErrorExportSignalDestinationNotSupport (ErrorCodeOffset-15)
#define | ErrorExportSignalDestinationReserved (ErrorCodeOffset-16)
#define | ErrorExportSignalCannotRepeatConfig (ErrorCodeOffset-17)
#define | ErrorExportSignalConfig (ErrorCodeOffset-18)
#define | ErrorPFIConfigFailed (ErrorCodeOffset-19)
#define | ErrorAWGStartFailed (ErrorCodeOffset-21)
#define | ErrorDataSourceSlectFailed (ErrorCodeOffset-22)
#define | ErrorDDSSignalFreConfigFailed (ErrorCodeOffset-23)
#define | ErrorControlLEDSetHighLowTicksFailed (ErrorCodeOffset-24)
#define | ErrorAWGStopFailed (ErrorCodeOffset-25)
#define | ErrorGetGenerationStatusFailed (ErrorCodeOffset-26)
#define | ErrorTxUnderflow (ErrorCodeOffset-27)
#define | ErrorCalcUpDownConverterParaFailed (ErrorCodeOffset-28)
#define | ErrorLMK048xxCalcPllParamFailed (ErrorCodeOffset-29)
#define | ErrorLMK048xxConfigPLLFailed (ErrorCodeOffset-30)
#define | ErrorAWGChannelDelayParam (ErrorCodeOffset-31)
#define | ErrorCalcMixerParamFailed (ErrorCodeOffset-32)
#define | ErrorTxClearFailed (ErrorCodeOffset-33)
#define | ErrorTxConfigBufferFailed (ErrorCodeOffset-34)
#define | ErrorTxConfigOutputStrobelFailed (ErrorCodeOffset-35)
#define | ErrorTxConfigGenerationFailed (ErrorCodeOffset-36)
#define | ErrorTxConfigSingleTransferBytesFailed (ErrorCodeOffset-37)
#define | ErrorTxConfigTriggerFailed (ErrorCodeOffset-38)
#define | ErrorRoutingMatrixConfigFailed (ErrorCodeOffset-39)
#define | ErrorDigitialGainParam (ErrorCodeOffset-40)
#define | ErrorTriggerTypeParam (ErrorCodeOffset-41)
#define | ErrorDigitalTriggerParam (ErrorCodeOffset-42)
#define | ErrorSendSoftwareTriggerFailed (ErrorCodeOffset-43)
#define | ErrorBufferLengthParam (ErrorCodeOffset-44)
#define | ErrorAWGDataSourceParam (ErrorCodeOffset-45)
#define | ErrorBITFrequencyParam (ErrorCodeOffset-46)
#define | ErrorSampleRateParam (ErrorCodeOffset-47)
#define | ErrorStandardWaveformChannelID (ErrorCodeOffset-48)
#define | ErrorStandardWaveformConfigFailed (ErrorCodeOffset-49)
#define | ErrorResetAXISInterfaceFailed (ErrorCodeOffset-50)
#define | ErrorDDSPhaseOffset (ErrorCodeOffset-51)
#define | ErrorInvalidCalibration (ErrorCodeOffset-52)
#define | ErrorNotSupportAWG (ErrorCodeOffset-53)
#define | ErrorEEPROMCalCRCFailed (ErrorCodeOffset-54)
#define | ErrorPLLNotLocked (ErrorCodeOffset-55)
#define | ErrorLMK048xxRefClkSource (ErrorCodeOffset-56)
#define | ErrorTaskIsStartDonotAllowConfig (ErrorCodeOffset-57)
#define | ErrorDILineCountInvalid (ErrorCodeOffset - 100)
#define | ErrorDILineInvalid (ErrorCodeOffset - 101)
#define | ErrorDOLineCountInvalid (ErrorCodeOffset - 102)
#define | ErrorDOLineInvalid (ErrorCodeOffset - 103)
#define | ErrorDIOStarted (ErrorCodeOffset - 104)
#define | ErrorDIONotStart (ErrorCodeOffset - 105)

Typedefs

typedef unsigned long long | UINT64
typedef unsigned char | BYTE
typedef void * | Handle

Enumerations

enum Routing_Matrix_0_IN {
PFI_0_OUT_0 = 8 , PFI_0_OUT_1 = 9 , PFI_0_OUT_2 = 10 , PFI_0_OUT_3 = 11 ,
PFI_0_OUT_4 = 12 , PFI_0_OUT_5 = 13 , PFI_0_OUT_6 = 14 , PFI_0_OUT_7 = 15 ,
PFI_PXI_Trig_OUT_0 = 16 , PFI_PXI_Trig_OUT_1 = 17 , PFI_PXI_Trig_OUT_2 = 18 , PFI_PXI_Trig_OUT_3 = 19 ,
PFI_PXI_Trig_OUT_4 = 20 , PFI_PXI_Trig_OUT_5 = 21 , PFI_PXI_Trig_OUT_6 = 22 , PFI_PXI_Trig_OUT_7 = 23 ,
ClkManager_0_divider_0_OUT = 3 , ClkManager_0_master_trigger_OUT = 4 , Standard_Waveform_0_sync_ch0_OUT = 24 , Standard_Waveform_0_sync_ch1_OUT = 25 ,
Tx_Engine_0_generation_done_OUT = 5 , Tx_Engine_0_ready_for_start_trigger_OUT = 2 , Tx_Engine_0_running_OUT = 6 , Tx_Engine_0_start_trigger_out_OUT = 1 ,
AXIS_Clk_OUT = 7 , PFI_Trigger_ui_0_0_di_OUT = 26 , ClkManager_0_trigger_valid_rst_OUT =27 , ClkManager_0_trigger_valid_rst_not_OUT = 28 ,
clk_from_pll_OUT =29 , constant_High_OUT =30 , pll_sync_OUT =31
}
enum Routing_Matrix_0_OUT {
PFI_0_IN_0 = 8 , PFI_0_IN_1 = 9 , PFI_0_IN_2 = 10 , PFI_0_IN_3 = 11 ,
PFI_0_IN_4 = 12 , PFI_0_IN_5 = 13 , PFI_0_IN_6 = 14 , PFI_0_IN_7 = 15 ,
PFI_PXI_Trig_IN_0 = 16 , PFI_PXI_Trig_IN_1 = 17 , PFI_PXI_Trig_IN_2 = 18 , PFI_PXI_Trig_IN_3 = 19 ,
PFI_PXI_Trig_IN_4 = 20 , PFI_PXI_Trig_IN_5 = 21 , PFI_PXI_Trig_IN_6 = 22 , PFI_PXI_Trig_IN_7 = 23 ,
ClkManager_0_trigger_in_IN = 0 , Tx_Engine_0_start_trigger_in_IN = 1 , Routing_Matrix_0_p_0_2_out_IN = 2 , PFI_Trigger_ui_0_0_do_IN = 3 ,
pll_sync_IN =4
}
enum DigitalTriggerSource {
TriggerIn = PFI_Trigger_ui_0_0_di_OUT , PFI_In_0 = PFI_0_OUT_0 , PFI_In_1 = PFI_0_OUT_1 , PFI_In_2 = PFI_0_OUT_2 ,
PFI_In_3 = PFI_0_OUT_3 , PFI_In_4 = PFI_0_OUT_4 , PFI_In_5 = PFI_0_OUT_5 , PFI_In_6 = PFI_0_OUT_6 ,
PFI_In_7 = PFI_0_OUT_7 , PXI_Trig_In_0 = PFI_PXI_Trig_OUT_0 , PXI_Trig_In_1 = PFI_PXI_Trig_OUT_1 , PXI_Trig_In_2 = PFI_PXI_Trig_OUT_2 ,
PXI_Trig_In_3 = PFI_PXI_Trig_OUT_3 , PXI_Trig_In_4 = PFI_PXI_Trig_OUT_4 , PXI_Trig_In_5 = PFI_PXI_Trig_OUT_5 , PXI_Trig_In_6 = PFI_PXI_Trig_OUT_6 ,
PXI_Trig_In_7 = PFI_PXI_Trig_OUT_7
}
enum ExportSignalSource {
AOReadyForStartTrigger = Tx_Engine_0_ready_for_start_trigger_OUT , AOStartTrigger = Tx_Engine_0_start_trigger_out_OUT , AOGenerationDone = Tx_Engine_0_generation_done_OUT , AORunning = Tx_Engine_0_running_OUT ,
AOSampleClk = clk_from_pll_OUT , Standard_Waveform_sync_ch0 =Standard_Waveform_0_sync_ch0_OUT , Standard_Waveform_sync_ch1 = Standard_Waveform_0_sync_ch1_OUT , Pll_Sync_Master_Trigger = ClkManager_0_master_trigger_OUT ,
Pll_Sync_Trigger_Valid = ClkManager_0_trigger_valid_rst_OUT , Pll_Sync_Trigger_Valid_Not = ClkManager_0_trigger_valid_rst_not_OUT , Pll_Sync = pll_sync_OUT
}
enum ExportSignalDestination {
TriggerOut = PFI_Trigger_ui_0_0_do_IN , PFI_Out_0 = PFI_0_IN_0 , PFI_Out_1 = PFI_0_IN_1 , PFI_Out_2 = PFI_0_IN_2 ,
PFI_Out_3 = PFI_0_IN_3 , PFI_Out_4 = PFI_0_IN_4 , PFI_Out_5 = PFI_0_IN_5 , PFI_Out_6 = PFI_0_IN_6 ,
PFI_Out_7 = PFI_0_IN_7 , PXI_Trig_Out0 = PFI_PXI_Trig_IN_0 , PXI_Trig_Out1 = PFI_PXI_Trig_IN_1 , PXI_Trig_Out2 = PFI_PXI_Trig_IN_2 ,
PXI_Trig_Out3 = PFI_PXI_Trig_IN_3 , PXI_Trig_Out4 = PFI_PXI_Trig_IN_4 , PXI_Trig_Out5 = PFI_PXI_Trig_IN_5 , PXI_Trig_Out6 = PFI_PXI_Trig_IN_6 ,
PXI_Trig_Out7 = PFI_PXI_Trig_IN_7
}
enum | GenerationMode { Finite = 0 , ContinuousWrapping = 1 , Stream = 2 }
enum | ExportClockType { None , SampleClk }
enum | AWGDataSource { AWGDataSourceDDS = 0 , AWGDataSourceSoftware = 1 }
enum | AWGOutputRange { AWGOutputRange_Disable = 1 , AWGOutputRange_1vpp = 5 , AWGOutputRange_2p5vpp = 6 , AWGOutputRange_10vpp = 10 }
enum | StandardWaveformType { Sine =0 , Square =1 , Triangle =2 }
enum | PllSyncMode { PllSyncModeSoftware =0 , PllSyncModeHardware =1 }
enum | AWGTriggerType { ImmediateTrigger = 0x0 , SoftTrigger = 0x1 , DigitalTrigger = 0x2 }
enum | RefClockSource { ClockSource_Local_VCO_10M = 0 , ClockSource_PXIe_Clk100 = 1 , ClockSource_External_Clk = 2 }
enum | SampleClockSource { SampleClockSource_Internal = 0 , SampleClockSource_External = 1 }
enum | PllWorkMode { PllWorkMode_Dual_Loop_With_Nested_Zero_Delay = 0 , PllWorkMode_Dual_Loop = 1 , PllWorkMode_PLL2_Single_Loop = 2 }
enum | DigitalTriggerCondition { Rising_Edge_Trigger = 2 , Falling_Edge_Trigger = 4 , High_Level_Trigger = 8 , Low_Level_Trigger = 16 }
enum | JY9702_DeviceProperty { JY9702_Independent = 0 , JY9702_MASTER = 1 , JY9702_SLAVE = 3 }

Functions

JYDLL_API int STDCALL | JY9702Core_GetDeviceList (JY9702DeviceInfo deviceInfo[], int deviceInfoLength)
获取所有设备 More...
JYDLL_API int STDCALL | JY9702Core_Open (int slotNumber, int *cardID)
打开设备 More...
JYDLL_API int STDCALL | JY9702Core_Open_WithAliasName (const char *aliasName, int *cardID)
打开设备 More...
JYDLL_API int STDCALL | JY9702Core_Close (int cardID)
关闭设备 More...
JYDLL_API int STDCALL | JY9702Core_GetTemperature (int cardID, double *fpgaTemp)
获取板卡温度 More...
JYDLL_API int STDCALL | JY9702Core_ConfigDeviceClock (int cardID, RefClockSource clockSource=ClockSource_Local_VCO_10M, double refClkFreq=10e6, PllWorkMode workMode=PllWorkMode_Dual_Loop, SampleClockSource sampleClockSource=SampleClockSource_Internal)
选择时钟源,默认内部时钟 More...
JYDLL_API int STDCALL | JY9702Core_GetLastError (int cardID, char *message, int *errorCode)
获取最后一条错误信息 More...
JYDLL_API int STDCALL | JY9702Core_ExportSignal (int cardID, ExportSignalSource source, ExportSignalDestination destination)
导出信号配置 More...
JYDLL_API int STDCALL | JY9702Core_ResetGPIO (int cardID)
将PFI，PXITrigger方向设置为输入，并且RoutingMatrix的所有输出信号连接到低电平 More...
JYDLL_API int STDCALL | JY9702Core_AWG_Init (int cardID)
初始化AO More...
JYDLL_API int STDCALL | JY9702Core_AWG_ConfigMultiBoardSync (int cardID, JY9702_DeviceProperty syncMode=JY9702_DeviceProperty::JY9702_Independent)
AWG,多卡同步 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetSlaveSamplaClkSyncTrigger (int cardID, DigitalTriggerSource syncTriggerSource=PXI_Trig_In_0)
AWG,多卡同步,设置Slave设备接收时钟同步信号来源 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SendSoftwareTrigger (int cardID)
AWG发送软件触发 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetEnabledChannels (int cardID, int channelMask)
AWG使能通道 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetGenerationMode (int cardID, GenerationMode generationMode)
AWG设置波形生成模式 More...
JYDLL_API int STDCALL | JY9702Core_AWG_ConfigPll (int cardID)
提交pll配置，多卡同步的时候，在JY9702Core_AWG_Commit前调用此api More...
JYDLL_API int STDCALL | JY9702Core_AWG_CheckPllStatus (int cardID)
查询pll状态，多卡同步的时候，在JY9702Core_AWG_Commit前调用此api More...
JYDLL_API int STDCALL | JY9702Core_AWG_Commit (int cardID)
提交配置 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetOutputRange (int cardID, AWGOutputRange ch0Range=AWGOutputRange_1vpp, AWGOutputRange ch1Range=AWGOutputRange_1vpp)
设置量程 More...
JYDLL_API int STDCALL | JY9702Core_AWG_Start (int cardID)
开始 More...
JYDLL_API int STDCALL | JY9702Core_AWG_Stop (int cardID)
停止 More...
JYDLL_API int STDCALL | JY9702Core_AWG_GetGenerationStatus (int cardID, bool *complete, unsigned long long *samplesGenerated, unsigned int *availableBufferLength)
获取生成状态 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetDigitalGain (int cardID, int channelMask, double digitalgain)
设置通道增益 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetTriggerType (int cardID, AWGTriggerType triggerType)
设置触发类型 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetDigitalTrigger (int cardID, DigitalTriggerCondition digitalTriggerType, DigitalTriggerSource digitalTriggerSource)
设置触发类型 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetSampleRate (int cardID, double sampleRate)
设置采样率 More...
JYDLL_API int STDCALL | JY9702Core_AWG_GetSampleRate (int cardID, double *sampleRate)
获取采样率 More...
JYDLL_API int STDCALL | JY9702Core_AWG_WriteDataBinary16 (int cardID, short *dataBuffer, unsigned int samplesToWrite, unsigned int *actualSamples, int timeout)
写数据，需要在commit之后调用此函数 More...
JYDLL_API int STDCALL | JY9702Core_AWG_WriteDbl64 (int cardID, double *dataBuffer, unsigned int samplesToWrite, unsigned int *actualSamples, int timeout)
写数据，需要在commit之后调用此函数 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetBufferLength (int cardID, unsigned int length)
设置缓冲区大小，连续环绕模式的时候，length必须等于写入数据的字节数 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetSamplesToWrite (int cardID, int samplesToWrite)
设置每个通道写入点数，有限点模式和连续环绕模式下有效 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetDataSource (int cardID, int channelMask, AWGDataSource dataSource)
设置数据源 More...
JYDLL_API int STDCALL | JY9702Core_AWG_ConfigDDS (int cardID, int channelID, StandardWaveformType type=Sine, double expectedFrequency=1e6, double amp=1.0, double offset=0, double duty=0.5, double phaseOffset=0, double phaseCompare=0)
BIT输出信号的频率 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetEnableInverseSinc (int cardID, bool enableInverseSinc=false, bool enbaleOverflowProtection=false)
是否使能FPGA的InverseSinc来补偿频响 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetEnableInterpolator (int cardID, bool enableInterpolator=true)
是否使能DAC内插（发生带限信号时使能） More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetChannelDelay (int cardID, double Ch0Delay, double Ch1Delay)
设置通道时延 More...
JYDLL_API int STDCALL | JY9702Core_AWG_GetChannelDelay (int cardID, double *Ch0Delay, double *Ch1Delay)
获取通道时延，commit之后调用此函数有效 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetBasebandModeEnabled (int cardID, int enabled)
设置是否使用基带模式。基带模式是指传输complex信号给DAC，使用DAC的DUC将基带信号上变频到指定频率。此时DAC只输出ch0 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetCenterFrequency (int cardID, int channelMask, double frequency)
设置DUC的中心频率 More...
JYDLL_API int STDCALL | JY9702Core_AWG_HardwareSyncClkOutPre (int cardID)
使用硬件同步lkm048xx的预操作 More...
JYDLL_API int STDCALL | JY9702Core_AWG_HardwareSyncClkOutPost (int cardID)
使用硬件同步lkm048xx的后操作 More...
JYDLL_API int STDCALL | JY9702Core_AWG_SetSyncClkMode (int cardID, PllSyncMode syncMode=PllSyncModeSoftware)
同步lkm048xx的方式,默认软件。使用硬件同步时，需要搭配JY9702Core_AWG_HardwareSyncClkOutPre，JY9702Core_AWG_ClkSyncSendSoftwareTrigger，JY9702Core_AWG_HardwareSyncClkOutPost使用 More...
JYDLL_API int STDCALL | JY9702_DI_AddLines (int cardID, unsigned char *lines, int lineCount)
Enabled DI channels. More...
JYDLL_API int STDCALL | JY9702_DI_Start (int cardID)
Start DI. More...
JYDLL_API int STDCALL | JY9702_DI_Stop (int cardID)
Stop DI. More...
JYDLL_API int | JY9702_DI_ReadSinglePoint (int cardID, bool *readValues, int lineID)
read single data from a single line by lineID defined.if the lineID == -1,read all line data.The data type is bool, one bool defined one line status. More...
JYDLL_API int | JY9702__DI_ReadSinglePoint_U8 (int cardID, unsigned char *readValues)
read single data for all line. More...
JYDLL_API int STDCALL | JY9702_DO_AddLines (int cardID, unsigned char *lines, int lineCount)
Enabled DO channels. More...
JYDLL_API int STDCALL | JY9702_DO_Start (int cardID)
Start DO. More...
JYDLL_API int STDCALL | JY9702_DO_Stop (int cardID)
Stop DO. More...
JYDLL_API int | JY9702_DO_WriteSinglePoint (int cardID, bool *writeValues, int lineID)
write single data for a single line by lineID defined.if the lineID == -1,write all line data.The data type is bool, one bool defined one line status. More...
JYDLL_API int | JY9702_DO_WriteSinglePoint_U8 (int cardID, unsigned char writeValue)
write single data for all line. More...

Macro Definition Documentation

◆ CCALL

#define CCALL

◆ ErrorAWGChannelDelayParam

#define ErrorAWGChannelDelayParam (ErrorCodeOffset-31)

◆ ErrorAWGDataSourceParam

#define ErrorAWGDataSourceParam (ErrorCodeOffset-45)

◆ ErrorAWGStartFailed

#define ErrorAWGStartFailed (ErrorCodeOffset-21)

◆ ErrorAWGStopFailed

#define ErrorAWGStopFailed (ErrorCodeOffset-25)

◆ ErrorBITFrequencyParam

#define ErrorBITFrequencyParam (ErrorCodeOffset-46)

◆ ErrorBufferLengthParam

#define ErrorBufferLengthParam (ErrorCodeOffset-44)

◆ ErrorCalcMixerParamFailed

#define ErrorCalcMixerParamFailed (ErrorCodeOffset-32)

◆ ErrorCalcUpDownConverterParaFailed

#define ErrorCalcUpDownConverterParaFailed (ErrorCodeOffset-28)

◆ ErrorCardNotOpened

#define ErrorCardNotOpened (ErrorCodeOffset-9)

◆ ErrorCardNumberNotExistInDeviceManager

#define ErrorCardNumberNotExistInDeviceManager (ErrorCodeOffset-3)

◆ ErrorChannelParam

#define ErrorChannelParam (ErrorCodeOffset-10)

◆ ErrorClockSource

#define ErrorClockSource (ErrorCodeOffset-13)

◆ ErrorCodeOffset

#define ErrorCodeOffset (int)(-11000)

◆ ErrorControlLEDSetHighLowTicksFailed

#define ErrorControlLEDSetHighLowTicksFailed (ErrorCodeOffset-24)

◆ ErrorDataSourceSlectFailed

#define ErrorDataSourceSlectFailed (ErrorCodeOffset-22)

◆ ErrorDDSPhaseOffset

#define ErrorDDSPhaseOffset (ErrorCodeOffset-51)

◆ ErrorDDSSignalFreConfigFailed

#define ErrorDDSSignalFreConfigFailed (ErrorCodeOffset-23)

◆ ErrorDigitalTriggerParam

#define ErrorDigitalTriggerParam (ErrorCodeOffset-42)

◆ ErrorDigitialGainParam

#define ErrorDigitialGainParam (ErrorCodeOffset-40)

◆ ErrorDILineCountInvalid

#define ErrorDILineCountInvalid (ErrorCodeOffset - 100)

◆ ErrorDILineInvalid

#define ErrorDILineInvalid (ErrorCodeOffset - 101)

◆ ErrorDIONotStart

#define ErrorDIONotStart (ErrorCodeOffset - 105)

◆ ErrorDIOStarted

#define ErrorDIOStarted (ErrorCodeOffset - 104)

◆ ErrorDOLineCountInvalid

#define ErrorDOLineCountInvalid (ErrorCodeOffset - 102)

◆ ErrorDOLineInvalid

#define ErrorDOLineInvalid (ErrorCodeOffset - 103)

◆ ErrorEEPROMCalCRCFailed

#define ErrorEEPROMCalCRCFailed (ErrorCodeOffset-54)

◆ ErrorExportSignalCannotRepeatConfig

#define ErrorExportSignalCannotRepeatConfig (ErrorCodeOffset-17)

◆ ErrorExportSignalConfig

#define ErrorExportSignalConfig (ErrorCodeOffset-18)

◆ ErrorExportSignalDestinationNotSupport

#define ErrorExportSignalDestinationNotSupport (ErrorCodeOffset-15)

◆ ErrorExportSignalDestinationReserved

#define ErrorExportSignalDestinationReserved (ErrorCodeOffset-16)

◆ ErrorGenerationModeParam

#define ErrorGenerationModeParam (ErrorCodeOffset-11)

◆ ErrorGetGenerationStatusFailed

#define ErrorGetGenerationStatusFailed (ErrorCodeOffset-26)

◆ ErrorInvalidCalibration

#define ErrorInvalidCalibration (ErrorCodeOffset-52)

◆ ErrorInvalidParam

#define ErrorInvalidParam (ErrorCodeOffset-1)

◆ ErrorLMK048xxCalcPllParamFailed

#define ErrorLMK048xxCalcPllParamFailed (ErrorCodeOffset-29)

◆ ErrorLMK048xxConfigPLLFailed

#define ErrorLMK048xxConfigPLLFailed (ErrorCodeOffset-30)

◆ ErrorLMK048xxGetLockStatusFailed

#define ErrorLMK048xxGetLockStatusFailed (ErrorCodeOffset-5)

◆ ErrorLMK048xxInitFailed

#define ErrorLMK048xxInitFailed (ErrorCodeOffset-4)

◆ ErrorLMK048xxNotLocked

#define ErrorLMK048xxNotLocked (ErrorCodeOffset-6)

◆ ErrorLMK048xxRefClkSource

#define ErrorLMK048xxRefClkSource (ErrorCodeOffset-56)

◆ ErrorNotSupportAWG

#define ErrorNotSupportAWG (ErrorCodeOffset-53)

◆ ErrorOpenDeviceFailed

#define ErrorOpenDeviceFailed (ErrorCodeOffset-2)

◆ ErrorPFIConfigFailed

#define ErrorPFIConfigFailed (ErrorCodeOffset-19)

◆ ErrorPLLNotLocked

#define ErrorPLLNotLocked (ErrorCodeOffset-55)

◆ ErrorPointerNotNull

#define ErrorPointerNotNull (ErrorCodeOffset-8)

◆ ErrorResetAXISInterfaceFailed

#define ErrorResetAXISInterfaceFailed (ErrorCodeOffset-50)

◆ ErrorRoutingMatrixConfigFailed

#define ErrorRoutingMatrixConfigFailed (ErrorCodeOffset-39)

◆ ErrorSampleRateParam

#define ErrorSampleRateParam (ErrorCodeOffset-47)

◆ ErrorSamplesParam

#define ErrorSamplesParam (ErrorCodeOffset-12)

◆ ErrorSendSoftwareTriggerFailed

#define ErrorSendSoftwareTriggerFailed (ErrorCodeOffset-43)

◆ ErrorStandardWaveformChannelID

#define ErrorStandardWaveformChannelID (ErrorCodeOffset-48)

◆ ErrorStandardWaveformConfigFailed

#define ErrorStandardWaveformConfigFailed (ErrorCodeOffset-49)

◆ ErrorTaskIsStartDonotAllowConfig

#define ErrorTaskIsStartDonotAllowConfig (ErrorCodeOffset-57)

◆ ErrorTriggerTypeParam

#define ErrorTriggerTypeParam (ErrorCodeOffset-41)

◆ ErrorTxClearFailed

#define ErrorTxClearFailed (ErrorCodeOffset-33)

◆ ErrorTxConfigBufferFailed

#define ErrorTxConfigBufferFailed (ErrorCodeOffset-34)

◆ ErrorTxConfigGenerationFailed

#define ErrorTxConfigGenerationFailed (ErrorCodeOffset-36)

◆ ErrorTxConfigOutputStrobelFailed

#define ErrorTxConfigOutputStrobelFailed (ErrorCodeOffset-35)

◆ ErrorTxConfigSingleTransferBytesFailed

#define ErrorTxConfigSingleTransferBytesFailed (ErrorCodeOffset-37)

◆ ErrorTxConfigTriggerFailed

#define ErrorTxConfigTriggerFailed (ErrorCodeOffset-38)

◆ ErrorTxInitFailed

#define ErrorTxInitFailed (ErrorCodeOffset-7)

◆ ErrorTxUnderflow

#define ErrorTxUnderflow (ErrorCodeOffset-27)

◆ ExternalClockFrequencyParam

#define ExternalClockFrequencyParam (ErrorCodeOffset-14)

◆ JYDLL_API

#define JYDLL_API

◆ JYFailed

#define JYFailed (-1)

◆ JYSuccess

#define JYSuccess (0)

◆ Lmk048xxCheckPllStatusCnt

#define Lmk048xxCheckPllStatusCnt (100)

◆ NoError

#define NoError (0)

无错误

◆ STDCALL [1/2]

#define STDCALL

FileName:JY9702Core.h Copyright NOTICE(版权声明) Copyright (c) 2017, JXINST All rights reserved.

Author: jytek @JYTEK Version 1.1.0 Date:2022-11-10 History:

< /summary>

Windows Linux

◆ STDCALL [2/2]

#define STDCALL

FileName:JY9702Core.h Copyright NOTICE(版权声明) Copyright (c) 2017, JXINST All rights reserved.

Author: jytek @JYTEK Version 1.1.0 Date:2022-11-10 History:

< /summary>

Windows Linux

Typedef Documentation

◆ BYTE

typedef unsigned char BYTE

◆ Handle

typedef void* Handle

◆ UINT64

typedef unsigned long long UINT64

Enumeration Type Documentation

◆ AWGDataSource

enum AWGDataSource
Enumerator
AWGDataSourceDDS
AWGDataSourceSoftware

◆ AWGOutputRange

enum AWGOutputRange
Enumerator
AWGOutputRange_Disable
AWGOutputRange_1vpp
AWGOutputRange_2p5vpp
AWGOutputRange_10vpp

◆ AWGTriggerType

enum AWGTriggerType
Enumerator
ImmediateTrigger
SoftTrigger
DigitalTrigger

◆ DigitalTriggerCondition

enum DigitalTriggerCondition
Enumerator
Rising_Edge_Trigger
Falling_Edge_Trigger
High_Level_Trigger
Low_Level_Trigger

◆ DigitalTriggerSource

enum DigitalTriggerSource
Enumerator
TriggerIn
PFI_In_0
PFI_In_1
PFI_In_2
PFI_In_3
PFI_In_4
PFI_In_5
PFI_In_6
PFI_In_7
PXI_Trig_In_0
PXI_Trig_In_1
PXI_Trig_In_2
PXI_Trig_In_3
PXI_Trig_In_4
PXI_Trig_In_5
PXI_Trig_In_6
PXI_Trig_In_7

◆ ExportClockType

enum ExportClockType
Enumerator
None
SampleClk

◆ ExportSignalDestination

enum ExportSignalDestination
Enumerator
TriggerOut
PFI_Out_0
PFI_Out_1
PFI_Out_2
PFI_Out_3
PFI_Out_4
PFI_Out_5
PFI_Out_6
PFI_Out_7
PXI_Trig_Out0
PXI_Trig_Out1
PXI_Trig_Out2
PXI_Trig_Out3
PXI_Trig_Out4
PXI_Trig_Out5
PXI_Trig_Out6
PXI_Trig_Out7

◆ ExportSignalSource

enum ExportSignalSource
Enumerator
AOReadyForStartTrigger
AOStartTrigger
AOGenerationDone
AORunning
AOSampleClk
Standard_Waveform_sync_ch0
Standard_Waveform_sync_ch1
Pll_Sync_Master_Trigger
Pll_Sync_Trigger_Valid
Pll_Sync_Trigger_Valid_Not
Pll_Sync

◆ GenerationMode

enum GenerationMode
Enumerator
Finite
ContinuousWrapping
Stream

◆ JY9702_DeviceProperty

enum JY9702_DeviceProperty
Enumerator
JY9702_Independent | Device as independent.
JY9702_MASTER | Device as master.
JY9702_SLAVE | Device as slave.

◆ PllSyncMode

enum PllSyncMode
Enumerator
PllSyncModeSoftware
PllSyncModeHardware

◆ PllWorkMode

enum PllWorkMode
Enumerator
PllWorkMode_Dual_Loop_With_Nested_Zero_Delay
PllWorkMode_Dual_Loop
PllWorkMode_PLL2_Single_Loop

◆ RefClockSource

enum RefClockSource
Enumerator
ClockSource_Local_VCO_10M
ClockSource_PXIe_Clk100
ClockSource_External_Clk

◆ Routing_Matrix_0_IN

enum Routing_Matrix_0_IN
Enumerator
PFI_0_OUT_0
PFI_0_OUT_1
PFI_0_OUT_2
PFI_0_OUT_3
PFI_0_OUT_4
PFI_0_OUT_5
PFI_0_OUT_6
PFI_0_OUT_7
PFI_PXI_Trig_OUT_0
PFI_PXI_Trig_OUT_1
PFI_PXI_Trig_OUT_2
PFI_PXI_Trig_OUT_3
PFI_PXI_Trig_OUT_4
PFI_PXI_Trig_OUT_5
PFI_PXI_Trig_OUT_6
PFI_PXI_Trig_OUT_7
ClkManager_0_divider_0_OUT
ClkManager_0_master_trigger_OUT
Standard_Waveform_0_sync_ch0_OUT
Standard_Waveform_0_sync_ch1_OUT
Tx_Engine_0_generation_done_OUT
Tx_Engine_0_ready_for_start_trigger_OUT
Tx_Engine_0_running_OUT
Tx_Engine_0_start_trigger_out_OUT
AXIS_Clk_OUT
PFI_Trigger_ui_0_0_di_OUT
ClkManager_0_trigger_valid_rst_OUT
ClkManager_0_trigger_valid_rst_not_OUT
clk_from_pll_OUT
constant_High_OUT
pll_sync_OUT

◆ Routing_Matrix_0_OUT

enum Routing_Matrix_0_OUT
Enumerator
PFI_0_IN_0
PFI_0_IN_1
PFI_0_IN_2
PFI_0_IN_3
PFI_0_IN_4
PFI_0_IN_5
PFI_0_IN_6
PFI_0_IN_7
PFI_PXI_Trig_IN_0
PFI_PXI_Trig_IN_1
PFI_PXI_Trig_IN_2
PFI_PXI_Trig_IN_3
PFI_PXI_Trig_IN_4
PFI_PXI_Trig_IN_5
PFI_PXI_Trig_IN_6
PFI_PXI_Trig_IN_7
ClkManager_0_trigger_in_IN
Tx_Engine_0_start_trigger_in_IN
Routing_Matrix_0_p_0_2_out_IN
PFI_Trigger_ui_0_0_do_IN
pll_sync_IN

◆ SampleClockSource

enum SampleClockSource
Enumerator
SampleClockSource_Internal
SampleClockSource_External

◆ StandardWaveformType

enum StandardWaveformType
Enumerator
Sine
Square
Triangle

Function Documentation

◆ JY9702__DI_ReadSinglePoint_U8()

JYDLL_API int JY9702__DI_ReadSinglePoint_U8 | ( | int | cardID,
 |  | unsigned char * | readValues
 | ) |  |

read single data for all line.

Parameters
cardID device handle
readValues read value,the char bit 1 to 7 defined the line 0 to line 7.
Returns
0 if success or other error code

◆ JY9702_DI_AddLines()

JYDLL_API int STDCALL JY9702_DI_AddLines | ( | int | cardID,
 |  | unsigned char * | lines,
 |  | int | lineCount
 | ) |  |

Enabled DI channels.

Parameters
cardID | device handle
lines | array[lineCount] containing line IDs
lineCount | number of lines to be enabled
Returns
0 if success or other error code

◆ JY9702_DI_ReadSinglePoint()

JYDLL_API int JY9702_DI_ReadSinglePoint | ( | int | cardID,
 |  | bool * | readValues,
 |  | int | lineID
 | ) |  |

read single data from a single line by lineID defined.if the lineID == -1,read all line data.The data type is bool, one bool defined one line status.

Parameters
cardID | device handle
readValues | read the specified line value. when the portID is -1, read all enabled lines values,the readValues Length must equal to lineCount(In function JY9702_DI_AddLines defined), and the values store in the add order of lines.
lineID | line number
Returns
0 if success or other error code

◆ JY9702_DI_Start()

JYDLL_API int STDCALL JY9702_DI_Start ( int cardID )

Start DI.

Parameters
cardID device handle
Returns
0 if success or other error code

◆ JY9702_DI_Stop()

JYDLL_API int STDCALL JY9702_DI_Stop ( int cardID )

Stop DI.

Parameters
cardID device handle
Returns
0 if success or other error code

◆ JY9702_DO_AddLines()

JYDLL_API int STDCALL JY9702_DO_AddLines | ( | int | cardID,
 |  | unsigned char * | lines,
 |  | int | lineCount
 | ) |  |

Enabled DO channels.

Parameters
cardID | device handle
lines | array[lineCount] containing line IDs
lineCount | number of lines to be enabled
Returns
0 if success or other error code

◆ JY9702_DO_Start()

JYDLL_API int STDCALL JY9702_DO_Start ( int cardID )

Start DO.

Parameters
cardID device handle
Returns
0 if success or other error code

◆ JY9702_DO_Stop()

JYDLL_API int STDCALL JY9702_DO_Stop ( int cardID )

Stop DO.

Parameters
cardID device handle
Returns
0 if success or other error code

◆ JY9702_DO_WriteSinglePoint()

JYDLL_API int JY9702_DO_WriteSinglePoint | ( | int | cardID,
 |  | bool * | writeValues,
 |  | int | lineID
 | ) |  |

write single data for a single line by lineID defined.if the lineID == -1,write all line data.The data type is bool, one bool defined one line status.

Parameters
cardID | device handle
writeValues | write the specified line value. when the portID is -1, write all enabled lines values,the writeValues Length must equal to lineCount(In function JY9702_DO_AddLines defined), and the values store in the add order of lines.
lineID | line number
Returns
0 if success or other error code

◆ JY9702_DO_WriteSinglePoint_U8()

JYDLL_API int JY9702_DO_WriteSinglePoint_U8 | ( | int | cardID,
 |  | unsigned char | writeValue
 | ) |  |

write single data for all line.

Parameters
cardID device handle
writeValue write value,the char bit 1 to 7 defined the line 0 to line 7.
Returns
0 if success or other error code

◆ JY9702Core_AWG_CheckPllStatus()

JYDLL_API int STDCALL JY9702Core_AWG_CheckPllStatus ( int cardID )

查询pll状态，多卡同步的时候，在JY9702Core_AWG_Commit前调用此api

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_Commit()

JYDLL_API int STDCALL JY9702Core_AWG_Commit ( int cardID )

提交配置

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_ConfigDDS()

JYDLL_API int STDCALL JY9702Core_AWG_ConfigDDS | ( | int | cardID,
 |  | int | channelID,
 |  | StandardWaveformType | type = Sine,
 |  | double | expectedFrequency = 1e6,
 |  | double | amp = 1.0,
 |  | double | offset = 0,
 |  | double | duty = 0.5,
 |  | double | phaseOffset = 0,
 |  | double | phaseCompare = 0
 | ) |  |

BIT输出信号的频率

Parameters
cardID | cardID
channelID | 1：CH0, 2: CH1, 3: CH0+CH1
type | 期望输出的波形类型
expectedFrequency | 期望通过DDS输出信号的频率
amp | 期望输出波形的归一化幅度
offset | 期望输出波形的归一化偏移
duty | 期望输出波形的占空比，只对方波和三角波有效
phaseOffset | 初始相位
phaseCompare | sync引脚输出高电平的门限
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_ConfigMultiBoardSync()

JYDLL_API int STDCALL JY9702Core_AWG_ConfigMultiBoardSync | ( | int | cardID,
 |  | JY9702_DeviceProperty | syncMode = JY9702_DeviceProperty::JY9702_Independent
 | ) |  |

AWG,多卡同步

Parameters
cardID | cardID
syncMode | 同步模式
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_ConfigPll()

JYDLL_API int STDCALL JY9702Core_AWG_ConfigPll ( int cardID )

提交pll配置，多卡同步的时候，在JY9702Core_AWG_Commit前调用此api

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_GetChannelDelay()

JYDLL_API int STDCALL JY9702Core_AWG_GetChannelDelay | ( | int | cardID,
 |  | double * | Ch0Delay,
 |  | double * | Ch1Delay
 | ) |  |

获取通道时延，commit之后调用此函数有效

Parameters
cardID | cardID
Ch0Delay | 通道0的时延，单位ns
Ch1Delay | 通道1的时延，单位ns
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_GetGenerationStatus()

JYDLL_API int STDCALL JY9702Core_AWG_GetGenerationStatus | ( | int | cardID,
 |  | bool * | complete,
 |  | unsigned long long * | samplesGenerated,
 |  | unsigned int * | availableBufferLength
 | ) |  |

获取生成状态

Parameters
cardID | cardID
complete | 是否完成
samplesGenerated | 生成的点数
availableBufferLength | 剩余缓存长度，单位sample
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_GetSampleRate()

JYDLL_API int STDCALL JY9702Core_AWG_GetSampleRate | ( | int | cardID,
 |  | double * | sampleRate
 | ) |  |

获取采样率

Parameters
cardID | cardID
sampleRate | 实际的采样率,调用commit之后有效
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_HardwareSyncClkOutPost()

JYDLL_API int STDCALL JY9702Core_AWG_HardwareSyncClkOutPost ( int cardID )

使用硬件同步lkm048xx的后操作

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_HardwareSyncClkOutPre()

JYDLL_API int STDCALL JY9702Core_AWG_HardwareSyncClkOutPre ( int cardID )

使用硬件同步lkm048xx的预操作

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_Init()

JYDLL_API int STDCALL JY9702Core_AWG_Init ( int cardID )

初始化AO

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SendSoftwareTrigger()

JYDLL_API int STDCALL JY9702Core_AWG_SendSoftwareTrigger ( int cardID )

AWG发送软件触发

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetBasebandModeEnabled()

JYDLL_API int STDCALL JY9702Core_AWG_SetBasebandModeEnabled | ( | int | cardID,
 |  | int | enabled
 | ) |  |

设置是否使用基带模式。基带模式是指传输complex信号给DAC，使用DAC的DUC将基带信号上变频到指定频率。此时DAC只输出ch0

Parameters
cardID | cardID
enabled | 是否使能基带模式:1使能，0：不使能
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetBufferLength()

JYDLL_API int STDCALL JY9702Core_AWG_SetBufferLength | ( | int | cardID,
 |  | unsigned int | length
 | ) |  |

设置缓冲区大小，连续环绕模式的时候，length必须等于写入数据的字节数

Parameters
cardID cardID

Parameters
length 长度,单位字节，不能超过512M
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetCenterFrequency()

JYDLL_API int STDCALL JY9702Core_AWG_SetCenterFrequency | ( | int | cardID,
 |  | int | channelMask,
 |  | double | frequency
 | ) |  |

设置DUC的中心频率

Parameters
cardID | cardID
channel | 通道掩码
frequency | 中心频率,使用DAC的DUC功能
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetChannelDelay()

JYDLL_API int STDCALL JY9702Core_AWG_SetChannelDelay | ( | int | cardID,
 |  | double | Ch0Delay,
 |  | double | Ch1Delay
 | ) |  |

设置通道时延

Parameters
cardID | cardID
Ch0Delay | 通道0的时延，单位ns
Ch1Delay | 通道1的时延，单位ns
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetDataSource()

JYDLL_API int STDCALL JY9702Core_AWG_SetDataSource | ( | int | cardID,
 |  | int | channelMask,
 |  | AWGDataSource | dataSource
 | ) |  |

设置数据源

Parameters
cardID | cardID
channelMask | 1：CH0, 2: CH1, 3: CH0+CH1
dataSource | 数据源,默认AWGDataSourceSoftware
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetDigitalGain()

JYDLL_API int STDCALL JY9702Core_AWG_SetDigitalGain | ( | int | cardID,
 |  | int | channelMask,
 |  | double | digitalgain
 | ) |  |

设置通道增益

Parameters
cardID | cardID
channelMask | 通道掩码
digitalgain | 通道增益，比如0.5代表输出信号幅度为输入信号的0.5倍，2.0代表输出信号幅度为输入信号的2倍
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetDigitalTrigger()

JYDLL_API int STDCALL JY9702Core_AWG_SetDigitalTrigger | ( | int | cardID,
 |  | DigitalTriggerCondition | digitalTriggerType,
 |  | DigitalTriggerSource | digitalTriggerSource
 | ) |  |

设置触发类型

Parameters
cardID | cardID
digitalTriggerType | 数字触发类型
digitalTriggerSource | 数字触发源
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetEnabledChannels()

JYDLL_API int STDCALL JY9702Core_AWG_SetEnabledChannels | ( | int | cardID,
 |  | int | channelMask
 | ) |  |

AWG使能通道

Parameters
cardID | cardID
channelMask | 二进制从低到高表示各通道，-1为所有通道
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetEnableInterpolator()

JYDLL_API int STDCALL JY9702Core_AWG_SetEnableInterpolator | ( | int | cardID,
 |  | bool | enableInterpolator = true
 | ) |  |

是否使能DAC内插（发生带限信号时使能）

Parameters
cardID | cardID
enableInterpolator | 是否使能DAC内插，默认是
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetEnableInverseSinc()

JYDLL_API int STDCALL JY9702Core_AWG_SetEnableInverseSinc | ( | int | cardID,
 |  | bool | enableInverseSinc = false,
 |  | bool | enbaleOverflowProtection = false
 | ) |  |

是否使能FPGA的InverseSinc来补偿频响

Parameters
cardID | cardID
enableInverseSinc | 是否使能FPGA的InverseSinc，默认否
enbaleOverflowProtection | 是否使能FPGA的enbaleOverflowProtection，默认否
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetGenerationMode()

JYDLL_API int STDCALL JY9702Core_AWG_SetGenerationMode | ( | int | cardID,
 |  | GenerationMode | generationMode
 | ) |  |

AWG设置波形生成模式

Parameters
cardID | cardID
generationMode | 波形生成模式
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetOutputRange()

JYDLL_API int STDCALL JY9702Core_AWG_SetOutputRange | ( | int | cardID,
 |  | AWGOutputRange | ch0Range = AWGOutputRange_1vpp,
 |  | AWGOutputRange | ch1Range = AWGOutputRange_1vpp
 | ) |  |

设置量程

Parameters
cardID | cardID
ch0Range | 通道0 量程
ch1Range | 通道1 量程
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetSampleRate()

JYDLL_API int STDCALL JY9702Core_AWG_SetSampleRate | ( | int | cardID,
 |  | double | sampleRate
 | ) |  |

设置采样率

Parameters
cardID | cardID
sampleRate | 期望的采样率
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetSamplesToWrite()

JYDLL_API int STDCALL JY9702Core_AWG_SetSamplesToWrite | ( | int | cardID,
 |  | int | samplesToWrite
 | ) |  |

设置每个通道写入点数，有限点模式和连续环绕模式下有效

Parameters
cardID | cardID
samplesToAcquire | 写入点数
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetSlaveSamplaClkSyncTrigger()

JYDLL_API int STDCALL JY9702Core_AWG_SetSlaveSamplaClkSyncTrigger | ( | int | cardID,
 |  | DigitalTriggerSource | syncTriggerSource = PXI_Trig_In_0
 | ) |  |

AWG,多卡同步,设置Slave设备接收时钟同步信号来源

Parameters
cardID | cardID
syncTriggerSource | 时钟同步信号源
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetSyncClkMode()

JYDLL_API int STDCALL JY9702Core_AWG_SetSyncClkMode | ( | int | cardID,
 |  | PllSyncMode | syncMode = PllSyncModeSoftware
 | ) |  |

同步lkm048xx的方式,默认软件。使用硬件同步时，需要搭配JY9702Core_AWG_HardwareSyncClkOutPre，JY9702Core_AWG_ClkSyncSendSoftwareTrigger，JY9702Core_AWG_HardwareSyncClkOutPost使用

Parameters
cardID | cardID
syncMode | sync方式：软件/硬件，多卡同步是需要选择硬件，单卡工作需要选择软件
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_SetTriggerType()

JYDLL_API int STDCALL JY9702Core_AWG_SetTriggerType | ( | int | cardID,
 |  | AWGTriggerType | triggerType
 | ) |  |

设置触发类型

Parameters
cardID | cardID
triggerType | 触发类型
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_Start()

JYDLL_API int STDCALL JY9702Core_AWG_Start ( int cardID )

开始

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_Stop()

JYDLL_API int STDCALL JY9702Core_AWG_Stop ( int cardID )

停止

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_WriteDataBinary16()

JYDLL_API int STDCALL JY9702Core_AWG_WriteDataBinary16 | ( | int | cardID,
 |  | short * | dataBuffer,
 |  | unsigned int | samplesToWrite,
 |  | unsigned int * | actualSamples,
 |  | int | timeout
 | ) |  |

写数据，需要在commit之后调用此函数

Parameters
cardID cardID

Parameters
dataBuffer | 数据指针
samplesToWrite | 每通道写的点数
timeout | 超时时间
Returns
成功 0；失败 ：错误码

◆ JY9702Core_AWG_WriteDbl64()

JYDLL_API int STDCALL JY9702Core_AWG_WriteDbl64 | ( | int | cardID,
 |  | double * | dataBuffer,
 |  | unsigned int | samplesToWrite,
 |  | unsigned int * | actualSamples,
 |  | int | timeout
 | ) |  |

写数据，需要在commit之后调用此函数

Parameters
cardID cardID

Parameters
dataBuffer | 数据指针
samplesToWrite | 每通道写的点数
timeout | 超时时间
Returns
成功 0；失败 ：错误码

◆ JY9702Core_Close()

JYDLL_API int STDCALL JY9702Core_Close ( int cardID )

关闭设备

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_ConfigDeviceClock()

JYDLL_API int STDCALL JY9702Core_ConfigDeviceClock | ( | int | cardID,
 |  | RefClockSource | clockSource = ClockSource_Local_VCO_10M,
 |  | double | refClkFreq = 10e6,
 |  | PllWorkMode | workMode = PllWorkMode_Dual_Loop,
 |  | SampleClockSource | sampleClockSource = SampleClockSource_Internal
 | ) |  |

选择时钟源,默认内部时钟

Parameters
cardID | cardID
clockSource | 参考时钟源
refClkFreq | 参考时钟频率，只有clockSource=ClockSource_External_Clk 时有效
workMode | 工作模式
sampleClkSource | sampleclk来源
Returns
成功 0；失败 ：错误码

◆ JY9702Core_ExportSignal()

JYDLL_API int STDCALL JY9702Core_ExportSignal | ( | int | cardID,
 |  | ExportSignalSource | source,
 |  | ExportSignalDestination | destination
 | ) |  |

导出信号配置

Parameters
cardID | cardID
source | 导出信号的源
destination | 导出信号的目标端口
Returns
成功 0；失败 ：错误码

◆ JY9702Core_GetDeviceList()

JYDLL_API int STDCALL JY9702Core_GetDeviceList | ( | JY9702DeviceInfo | deviceInfo[],
 |  | int | deviceInfoLength
 | ) |  |

获取所有设备

Parameters
deviceInfo | 卡槽号
deviceInfoLength | cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_GetLastError()

JYDLL_API int STDCALL JY9702Core_GetLastError | ( | int | cardID,
 |  | char * | message,
 |  | int * | errorCode
 | ) |  |

获取最后一条错误信息

Parameters
cardID | cardID
message | 最后一条错误信息
errorCode | 错误信息对应的错误码
Returns
大于等于0：错误信息字符串的长度；小于零：错误代码

◆ JY9702Core_GetTemperature()

JYDLL_API int STDCALL JY9702Core_GetTemperature | ( | int | cardID,
 |  | double * | fpgaTemp
 | ) |  |

获取板卡温度

Parameters
cardID | cardID
fpgaTem | FPGA芯片内部温度
Returns
成功 0；失败 ：错误码

<created>yasing,2019/5/8</created> <changed>yasing,2019/5/8</changed>

◆ JY9702Core_Open()

JYDLL_API int STDCALL JY9702Core_Open | ( | int | slotNumber,
 |  | int * | cardID
 | ) |  |

打开设备

Parameters
slotNumber | 卡槽号
cardID | cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_Open_WithAliasName()

JYDLL_API int STDCALL JY9702Core_Open_WithAliasName | ( | const char * | aliasName,
 |  | int * | cardID
 | ) |  |

打开设备

Parameters
aliasName | 设备别名
cardID | cardID
Returns
成功 0；失败 ：错误码

◆ JY9702Core_ResetGPIO()

JYDLL_API int STDCALL JY9702Core_ResetGPIO ( int cardID )

将PFI，PXITrigger方向设置为输入，并且RoutingMatrix的所有输出信号连接到低电平

Parameters
cardID cardID
Returns
成功 0；失败 ：错误码


9702 C++ Programming Manual: JY9702CoreDeviceInfo Struct Reference

Public Attributes | List of all members
JY9702CoreDeviceInfo Struct Reference

#include <JY9702Core.h>

Public Attributes

short | StartSentinel
short | EEPROMSize
short | CalibrationAddr
char | SerialNumber [10]
char | Model [8]
unsigned char | HWRev
short | ProductionDate
unsigned char | Reserved [5]

Member Data Documentation

◆ CalibrationAddr

short JY9702CoreDeviceInfo::CalibrationAddr

◆ EEPROMSize

short JY9702CoreDeviceInfo::EEPROMSize

◆ HWRev

unsigned char JY9702CoreDeviceInfo::HWRev

◆ Model

char JY9702CoreDeviceInfo::Model[8]

◆ ProductionDate

short JY9702CoreDeviceInfo::ProductionDate

◆ Reserved

unsigned char JY9702CoreDeviceInfo::Reserved[5]

◆ SerialNumber

char JY9702CoreDeviceInfo::SerialNumber[10]

◆ StartSentinel

short JY9702CoreDeviceInfo::StartSentinel
The documentation for this struct was generated from the following file:
  • D:/9702/Cpp/JY9702Core.h


9702 C++ Programming Manual: JY9702CoreCalibrationConstant Struct Reference

Public Attributes | List of all members
JY9702CoreCalibrationConstant Struct Reference

#include <JY9702Core.h>

Public Attributes

float | AWG_CH0_FS_mA_Range1Vpp
float | AWG_CH1_FS_mA_Range1Vpp
float | AWG_CH0_FS_mA_Range2p5Vpp
float | AWG_CH1_FS_mA_Range2p5Vpp
float | AWG_CH0_FS_mA_Range10Vpp
float | AWG_CH1_FS_mA_Range10Vpp
float | AWG_CH0_Offset_Range1Vpp
float | AWG_CH1_Offset_Range1Vpp
float | AWG_CH0_Offset_Range2p5Vpp
float | AWG_CH1_Offset_Range2p5Vpp
float | AWG_CH0_Offset_Range10Vpp
float | AWG_CH1_Offset_Range10Vpp

Member Data Documentation

◆ AWG_CH0_FS_mA_Range10Vpp

float JY9702CoreCalibrationConstant::AWG_CH0_FS_mA_Range10Vpp

◆ AWG_CH0_FS_mA_Range1Vpp

float JY9702CoreCalibrationConstant::AWG_CH0_FS_mA_Range1Vpp

◆ AWG_CH0_FS_mA_Range2p5Vpp

float JY9702CoreCalibrationConstant::AWG_CH0_FS_mA_Range2p5Vpp

◆ AWG_CH0_Offset_Range10Vpp

float JY9702CoreCalibrationConstant::AWG_CH0_Offset_Range10Vpp

◆ AWG_CH0_Offset_Range1Vpp

float JY9702CoreCalibrationConstant::AWG_CH0_Offset_Range1Vpp

◆ AWG_CH0_Offset_Range2p5Vpp

float JY9702CoreCalibrationConstant::AWG_CH0_Offset_Range2p5Vpp

◆ AWG_CH1_FS_mA_Range10Vpp

float JY9702CoreCalibrationConstant::AWG_CH1_FS_mA_Range10Vpp

◆ AWG_CH1_FS_mA_Range1Vpp

float JY9702CoreCalibrationConstant::AWG_CH1_FS_mA_Range1Vpp

◆ AWG_CH1_FS_mA_Range2p5Vpp

float JY9702CoreCalibrationConstant::AWG_CH1_FS_mA_Range2p5Vpp

◆ AWG_CH1_Offset_Range10Vpp

float JY9702CoreCalibrationConstant::AWG_CH1_Offset_Range10Vpp

◆ AWG_CH1_Offset_Range1Vpp

float JY9702CoreCalibrationConstant::AWG_CH1_Offset_Range1Vpp

◆ AWG_CH1_Offset_Range2p5Vpp

float JY9702CoreCalibrationConstant::AWG_CH1_Offset_Range2p5Vpp
The documentation for this struct was generated from the following file:
  • D:/9702/Cpp/JY9702Core.h


9702 C++ Programming Manual: JY9702CoreCalibrationInfo Struct Reference

Public Attributes | List of all members
JY9702CoreCalibrationInfo Struct Reference

#include <JY9702Core.h>

Public Attributes

short | PreRegionAddress =0
short | NextRegionAddress =0
short | CurrentRegionSize = sizeof(JY9702CoreCalibrationConstant)+17
char | RegionType =0
short | CalibrationTimeStamp
short | CalibrationTemperature
short | CalibrationDataAddress = 0x11
short | CalibrationSize = sizeof(JY9702CoreCalibrationConstant)
unsigned short | CalibrationCRC16
JY9702CoreCalibrationConstant CalibrationInfo

Member Data Documentation

◆ CalibrationCRC16

unsigned short JY9702CoreCalibrationInfo::CalibrationCRC16

◆ CalibrationDataAddress

short JY9702CoreCalibrationInfo::CalibrationDataAddress = 0x11

◆ CalibrationInfo

JY9702CoreCalibrationConstant JY9702CoreCalibrationInfo::CalibrationInfo

◆ CalibrationSize

short JY9702CoreCalibrationInfo::CalibrationSize = sizeof(JY9702CoreCalibrationConstant)

◆ CalibrationTemperature

short JY9702CoreCalibrationInfo::CalibrationTemperature

◆ CalibrationTimeStamp

short JY9702CoreCalibrationInfo::CalibrationTimeStamp

◆ CurrentRegionSize

short JY9702CoreCalibrationInfo::CurrentRegionSize = sizeof(JY9702CoreCalibrationConstant)+17

◆ NextRegionAddress

short JY9702CoreCalibrationInfo::NextRegionAddress =0

◆ PreRegionAddress

short JY9702CoreCalibrationInfo::PreRegionAddress =0

◆ RegionType

char JY9702CoreCalibrationInfo::RegionType =0
The documentation for this struct was generated from the following file:
  • D:/9702/Cpp/JY9702Core.h


9702 C++ Programming Manual: JY9702DeviceInfo Struct Reference

Public Attributes | List of all members
JY9702DeviceInfo Struct Reference

#include <JY9702Core.h>

Public Attributes

char | aliasName [64]
int | slotNumber
char | serialNumber [33]
char | model [65]
char | HardwareVer [16]
char | FirmwareVer [16]
char | FrameworkVer [16]
char | DriverSetVer [16]
char | ProductionDate [16]

Member Data Documentation

◆ aliasName

char JY9702DeviceInfo::aliasName[64]

◆ DriverSetVer

char JY9702DeviceInfo::DriverSetVer[16]

◆ FirmwareVer

char JY9702DeviceInfo::FirmwareVer[16]

◆ FrameworkVer

char JY9702DeviceInfo::FrameworkVer[16]

◆ HardwareVer

char JY9702DeviceInfo::HardwareVer[16]

◆ model

char JY9702DeviceInfo::model[65]

◆ ProductionDate

char JY9702DeviceInfo::ProductionDate[16]

◆ serialNumber

char JY9702DeviceInfo::serialNumber[33]

◆ slotNumber

int JY9702DeviceInfo::slotNumber
The documentation for this struct was generated from the following file:
  • D:/9702/Cpp/JY9702Core.h


9702 C++ Programming Manual: Class List

Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C JY9702CoreCalibrationConstant
C JY9702CoreCalibrationInfo
C JY9702CoreDeviceInfo
C JY9702DeviceInfo


9702 C++ Programming Manual: Class Index

Class Index
J
J
JY9702CoreCalibrationConstant
JY9702CoreCalibrationInfo
JY9702CoreDeviceInfo
JY9702DeviceInfo


9702 C++ Programming Manual: D: Directory Reference

  • D:
D: Directory Reference

Directories

directory 9702


9702 C++ Programming Manual: D:/9702 Directory Reference

  • D:
  • 9702
9702 Directory Reference

Directories

directory Cpp


9702 C++ Programming Manual: File List

File List
Here is a list of all files with brief descriptions:
[detail level 1234]
▼ D:
▼ 9702
▼ Cpp
JY9702Core.h


9702 C++ Programming Manual: Class Members

Here is a list of all class members with links to the classes they belong to:

- a -

  • aliasName : JY9702DeviceInfo
  • AWG_CH0_FS_mA_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_FS_mA_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_FS_mA_Range2p5Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_Offset_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_Offset_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_Offset_Range2p5Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_FS_mA_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_FS_mA_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_FS_mA_Range2p5Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_Offset_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_Offset_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_Offset_Range2p5Vpp : JY9702CoreCalibrationConstant

- c -

  • CalibrationAddr : JY9702CoreDeviceInfo
  • CalibrationCRC16 : JY9702CoreCalibrationInfo
  • CalibrationDataAddress : JY9702CoreCalibrationInfo
  • CalibrationInfo : JY9702CoreCalibrationInfo
  • CalibrationSize : JY9702CoreCalibrationInfo
  • CalibrationTemperature : JY9702CoreCalibrationInfo
  • CalibrationTimeStamp : JY9702CoreCalibrationInfo
  • CurrentRegionSize : JY9702CoreCalibrationInfo

- d -

  • DriverSetVer : JY9702DeviceInfo

- e -

  • EEPROMSize : JY9702CoreDeviceInfo

- f -

  • FirmwareVer : JY9702DeviceInfo
  • FrameworkVer : JY9702DeviceInfo

- h -

  • HardwareVer : JY9702DeviceInfo
  • HWRev : JY9702CoreDeviceInfo

- m -

  • Model : JY9702CoreDeviceInfo
  • model : JY9702DeviceInfo

- n -

  • NextRegionAddress : JY9702CoreCalibrationInfo

- p -

  • PreRegionAddress : JY9702CoreCalibrationInfo
  • ProductionDate : JY9702CoreDeviceInfo , JY9702DeviceInfo

- r -

  • RegionType : JY9702CoreCalibrationInfo
  • Reserved : JY9702CoreDeviceInfo

- s -

  • SerialNumber : JY9702CoreDeviceInfo
  • serialNumber : JY9702DeviceInfo
  • slotNumber : JY9702DeviceInfo
  • StartSentinel : JY9702CoreDeviceInfo


9702 C++ Programming Manual: Class Members - Variables

- a -

  • aliasName : JY9702DeviceInfo
  • AWG_CH0_FS_mA_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_FS_mA_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_FS_mA_Range2p5Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_Offset_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_Offset_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH0_Offset_Range2p5Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_FS_mA_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_FS_mA_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_FS_mA_Range2p5Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_Offset_Range10Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_Offset_Range1Vpp : JY9702CoreCalibrationConstant
  • AWG_CH1_Offset_Range2p5Vpp : JY9702CoreCalibrationConstant

- c -

  • CalibrationAddr : JY9702CoreDeviceInfo
  • CalibrationCRC16 : JY9702CoreCalibrationInfo
  • CalibrationDataAddress : JY9702CoreCalibrationInfo
  • CalibrationInfo : JY9702CoreCalibrationInfo
  • CalibrationSize : JY9702CoreCalibrationInfo
  • CalibrationTemperature : JY9702CoreCalibrationInfo
  • CalibrationTimeStamp : JY9702CoreCalibrationInfo
  • CurrentRegionSize : JY9702CoreCalibrationInfo

- d -

  • DriverSetVer : JY9702DeviceInfo

- e -

  • EEPROMSize : JY9702CoreDeviceInfo

- f -

  • FirmwareVer : JY9702DeviceInfo
  • FrameworkVer : JY9702DeviceInfo

- h -

  • HardwareVer : JY9702DeviceInfo
  • HWRev : JY9702CoreDeviceInfo

- m -

  • Model : JY9702CoreDeviceInfo
  • model : JY9702DeviceInfo

- n -

  • NextRegionAddress : JY9702CoreCalibrationInfo

- p -

  • PreRegionAddress : JY9702CoreCalibrationInfo
  • ProductionDate : JY9702CoreDeviceInfo , JY9702DeviceInfo

- r -

  • RegionType : JY9702CoreCalibrationInfo
  • Reserved : JY9702CoreDeviceInfo

- s -

  • SerialNumber : JY9702CoreDeviceInfo
  • serialNumber : JY9702DeviceInfo
  • slotNumber : JY9702DeviceInfo
  • StartSentinel : JY9702CoreDeviceInfo


9702 C++ Programming Manual: File Members

Here is a list of all file members with links to the files they belong to:

- a -

  • AOGenerationDone : JY9702Core.h
  • AOReadyForStartTrigger : JY9702Core.h
  • AORunning : JY9702Core.h
  • AOSampleClk : JY9702Core.h
  • AOStartTrigger : JY9702Core.h
  • AWGDataSource : JY9702Core.h
  • AWGDataSourceDDS : JY9702Core.h
  • AWGDataSourceSoftware : JY9702Core.h
  • AWGOutputRange : JY9702Core.h
  • AWGOutputRange_10vpp : JY9702Core.h
  • AWGOutputRange_1vpp : JY9702Core.h
  • AWGOutputRange_2p5vpp : JY9702Core.h
  • AWGOutputRange_Disable : JY9702Core.h
  • AWGTriggerType : JY9702Core.h
  • AXIS_Clk_OUT : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- b -

  • BYTE : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- c -

  • CCALL : JY9702Core.h
  • clk_from_pll_OUT : JY9702Core.h
  • ClkManager_0_divider_0_OUT : JY9702Core.h
  • ClkManager_0_master_trigger_OUT : JY9702Core.h
  • ClkManager_0_trigger_in_IN : JY9702Core.h
  • ClkManager_0_trigger_valid_rst_not_OUT : JY9702Core.h
  • ClkManager_0_trigger_valid_rst_OUT : JY9702Core.h
  • ClockSource_External_Clk : JY9702Core.h
  • ClockSource_Local_VCO_10M : JY9702Core.h
  • ClockSource_PXIe_Clk100 : JY9702Core.h
  • constant_High_OUT : JY9702Core.h
  • ContinuousWrapping : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- d -

  • DigitalTrigger : JY9702Core.h
  • DigitalTriggerCondition : JY9702Core.h
  • DigitalTriggerSource : JY9702Core.h


- c -

  • CCALL : JY9702Core.h

- e -

  • ErrorAWGChannelDelayParam : JY9702Core.h
  • ErrorAWGDataSourceParam : JY9702Core.h
  • ErrorAWGStartFailed : JY9702Core.h
  • ErrorAWGStopFailed : JY9702Core.h
  • ErrorBITFrequencyParam : JY9702Core.h
  • ErrorBufferLengthParam : JY9702Core.h
  • ErrorCalcMixerParamFailed : JY9702Core.h
  • ErrorCalcUpDownConverterParaFailed : JY9702Core.h
  • ErrorCardNotOpened : JY9702Core.h
  • ErrorCardNumberNotExistInDeviceManager : JY9702Core.h
  • ErrorChannelParam : JY9702Core.h
  • ErrorClockSource : JY9702Core.h
  • ErrorCodeOffset : JY9702Core.h
  • ErrorControlLEDSetHighLowTicksFailed : JY9702Core.h
  • ErrorDataSourceSlectFailed : JY9702Core.h
  • ErrorDDSPhaseOffset : JY9702Core.h
  • ErrorDDSSignalFreConfigFailed : JY9702Core.h
  • ErrorDigitalTriggerParam : JY9702Core.h
  • ErrorDigitialGainParam : JY9702Core.h
  • ErrorDILineCountInvalid : JY9702Core.h
  • ErrorDILineInvalid : JY9702Core.h
  • ErrorDIONotStart : JY9702Core.h
  • ErrorDIOStarted : JY9702Core.h
  • ErrorDOLineCountInvalid : JY9702Core.h
  • ErrorDOLineInvalid : JY9702Core.h
  • ErrorEEPROMCalCRCFailed : JY9702Core.h
  • ErrorExportSignalCannotRepeatConfig : JY9702Core.h
  • ErrorExportSignalConfig : JY9702Core.h
  • ErrorExportSignalDestinationNotSupport : JY9702Core.h
  • ErrorExportSignalDestinationReserved : JY9702Core.h
  • ErrorGenerationModeParam : JY9702Core.h
  • ErrorGetGenerationStatusFailed : JY9702Core.h
  • ErrorInvalidCalibration : JY9702Core.h
  • ErrorInvalidParam : JY9702Core.h
  • ErrorLMK048xxCalcPllParamFailed : JY9702Core.h
  • ErrorLMK048xxConfigPLLFailed : JY9702Core.h
  • ErrorLMK048xxGetLockStatusFailed : JY9702Core.h
  • ErrorLMK048xxInitFailed : JY9702Core.h
  • ErrorLMK048xxNotLocked : JY9702Core.h
  • ErrorLMK048xxRefClkSource : JY9702Core.h
  • ErrorNotSupportAWG : JY9702Core.h
  • ErrorOpenDeviceFailed : JY9702Core.h
  • ErrorPFIConfigFailed : JY9702Core.h
  • ErrorPLLNotLocked : JY9702Core.h
  • ErrorPointerNotNull : JY9702Core.h
  • ErrorResetAXISInterfaceFailed : JY9702Core.h
  • ErrorRoutingMatrixConfigFailed : JY9702Core.h
  • ErrorSampleRateParam : JY9702Core.h
  • ErrorSamplesParam : JY9702Core.h
  • ErrorSendSoftwareTriggerFailed : JY9702Core.h
  • ErrorStandardWaveformChannelID : JY9702Core.h
  • ErrorStandardWaveformConfigFailed : JY9702Core.h
  • ErrorTaskIsStartDonotAllowConfig : JY9702Core.h
  • ErrorTriggerTypeParam : JY9702Core.h
  • ErrorTxClearFailed : JY9702Core.h
  • ErrorTxConfigBufferFailed : JY9702Core.h
  • ErrorTxConfigGenerationFailed : JY9702Core.h
  • ErrorTxConfigOutputStrobelFailed : JY9702Core.h
  • ErrorTxConfigSingleTransferBytesFailed : JY9702Core.h
  • ErrorTxConfigTriggerFailed : JY9702Core.h
  • ErrorTxInitFailed : JY9702Core.h
  • ErrorTxUnderflow : JY9702Core.h
  • ExternalClockFrequencyParam : JY9702Core.h

- j -

  • JYDLL_API : JY9702Core.h
  • JYFailed : JY9702Core.h
  • JYSuccess : JY9702Core.h

- l -

  • Lmk048xxCheckPllStatusCnt : JY9702Core.h

- n -

  • NoError : JY9702Core.h

- s -

  • STDCALL : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- e -

  • ErrorAWGChannelDelayParam : JY9702Core.h
  • ErrorAWGDataSourceParam : JY9702Core.h
  • ErrorAWGStartFailed : JY9702Core.h
  • ErrorAWGStopFailed : JY9702Core.h
  • ErrorBITFrequencyParam : JY9702Core.h
  • ErrorBufferLengthParam : JY9702Core.h
  • ErrorCalcMixerParamFailed : JY9702Core.h
  • ErrorCalcUpDownConverterParaFailed : JY9702Core.h
  • ErrorCardNotOpened : JY9702Core.h
  • ErrorCardNumberNotExistInDeviceManager : JY9702Core.h
  • ErrorChannelParam : JY9702Core.h
  • ErrorClockSource : JY9702Core.h
  • ErrorCodeOffset : JY9702Core.h
  • ErrorControlLEDSetHighLowTicksFailed : JY9702Core.h
  • ErrorDataSourceSlectFailed : JY9702Core.h
  • ErrorDDSPhaseOffset : JY9702Core.h
  • ErrorDDSSignalFreConfigFailed : JY9702Core.h
  • ErrorDigitalTriggerParam : JY9702Core.h
  • ErrorDigitialGainParam : JY9702Core.h
  • ErrorDILineCountInvalid : JY9702Core.h
  • ErrorDILineInvalid : JY9702Core.h
  • ErrorDIONotStart : JY9702Core.h
  • ErrorDIOStarted : JY9702Core.h
  • ErrorDOLineCountInvalid : JY9702Core.h
  • ErrorDOLineInvalid : JY9702Core.h
  • ErrorEEPROMCalCRCFailed : JY9702Core.h
  • ErrorExportSignalCannotRepeatConfig : JY9702Core.h
  • ErrorExportSignalConfig : JY9702Core.h
  • ErrorExportSignalDestinationNotSupport : JY9702Core.h
  • ErrorExportSignalDestinationReserved : JY9702Core.h
  • ErrorGenerationModeParam : JY9702Core.h
  • ErrorGetGenerationStatusFailed : JY9702Core.h
  • ErrorInvalidCalibration : JY9702Core.h
  • ErrorInvalidParam : JY9702Core.h
  • ErrorLMK048xxCalcPllParamFailed : JY9702Core.h
  • ErrorLMK048xxConfigPLLFailed : JY9702Core.h
  • ErrorLMK048xxGetLockStatusFailed : JY9702Core.h
  • ErrorLMK048xxInitFailed : JY9702Core.h
  • ErrorLMK048xxNotLocked : JY9702Core.h
  • ErrorLMK048xxRefClkSource : JY9702Core.h
  • ErrorNotSupportAWG : JY9702Core.h
  • ErrorOpenDeviceFailed : JY9702Core.h
  • ErrorPFIConfigFailed : JY9702Core.h
  • ErrorPLLNotLocked : JY9702Core.h
  • ErrorPointerNotNull : JY9702Core.h
  • ErrorResetAXISInterfaceFailed : JY9702Core.h
  • ErrorRoutingMatrixConfigFailed : JY9702Core.h
  • ErrorSampleRateParam : JY9702Core.h
  • ErrorSamplesParam : JY9702Core.h
  • ErrorSendSoftwareTriggerFailed : JY9702Core.h
  • ErrorStandardWaveformChannelID : JY9702Core.h
  • ErrorStandardWaveformConfigFailed : JY9702Core.h
  • ErrorTaskIsStartDonotAllowConfig : JY9702Core.h
  • ErrorTriggerTypeParam : JY9702Core.h
  • ErrorTxClearFailed : JY9702Core.h
  • ErrorTxConfigBufferFailed : JY9702Core.h
  • ErrorTxConfigGenerationFailed : JY9702Core.h
  • ErrorTxConfigOutputStrobelFailed : JY9702Core.h
  • ErrorTxConfigSingleTransferBytesFailed : JY9702Core.h
  • ErrorTxConfigTriggerFailed : JY9702Core.h
  • ErrorTxInitFailed : JY9702Core.h
  • ErrorTxUnderflow : JY9702Core.h
  • ExportClockType : JY9702Core.h
  • ExportSignalDestination : JY9702Core.h
  • ExportSignalSource : JY9702Core.h
  • ExternalClockFrequencyParam : JY9702Core.h


  • AWGDataSource : JY9702Core.h
  • AWGOutputRange : JY9702Core.h
  • AWGTriggerType : JY9702Core.h
  • DigitalTriggerCondition : JY9702Core.h
  • DigitalTriggerSource : JY9702Core.h
  • ExportClockType : JY9702Core.h
  • ExportSignalDestination : JY9702Core.h
  • ExportSignalSource : JY9702Core.h
  • GenerationMode : JY9702Core.h
  • JY9702_DeviceProperty : JY9702Core.h
  • PllSyncMode : JY9702Core.h
  • PllWorkMode : JY9702Core.h
  • RefClockSource : JY9702Core.h
  • Routing_Matrix_0_IN : JY9702Core.h
  • Routing_Matrix_0_OUT : JY9702Core.h
  • SampleClockSource : JY9702Core.h
  • StandardWaveformType : JY9702Core.h


- a -

  • AOGenerationDone : JY9702Core.h
  • AOReadyForStartTrigger : JY9702Core.h
  • AORunning : JY9702Core.h
  • AOSampleClk : JY9702Core.h
  • AOStartTrigger : JY9702Core.h
  • AWGDataSourceDDS : JY9702Core.h
  • AWGDataSourceSoftware : JY9702Core.h
  • AWGOutputRange_10vpp : JY9702Core.h
  • AWGOutputRange_1vpp : JY9702Core.h
  • AWGOutputRange_2p5vpp : JY9702Core.h
  • AWGOutputRange_Disable : JY9702Core.h
  • AXIS_Clk_OUT : JY9702Core.h

- c -

  • clk_from_pll_OUT : JY9702Core.h
  • ClkManager_0_divider_0_OUT : JY9702Core.h
  • ClkManager_0_master_trigger_OUT : JY9702Core.h
  • ClkManager_0_trigger_in_IN : JY9702Core.h
  • ClkManager_0_trigger_valid_rst_not_OUT : JY9702Core.h
  • ClkManager_0_trigger_valid_rst_OUT : JY9702Core.h
  • ClockSource_External_Clk : JY9702Core.h
  • ClockSource_Local_VCO_10M : JY9702Core.h
  • ClockSource_PXIe_Clk100 : JY9702Core.h
  • constant_High_OUT : JY9702Core.h
  • ContinuousWrapping : JY9702Core.h

- d -

  • DigitalTrigger : JY9702Core.h

- f -

  • Falling_Edge_Trigger : JY9702Core.h
  • Finite : JY9702Core.h

- h -

  • High_Level_Trigger : JY9702Core.h

- i -

  • ImmediateTrigger : JY9702Core.h

- j -

  • JY9702_Independent : JY9702Core.h
  • JY9702_MASTER : JY9702Core.h
  • JY9702_SLAVE : JY9702Core.h

- l -

  • Low_Level_Trigger : JY9702Core.h

- n -

  • None : JY9702Core.h

- p -

  • PFI_0_IN_0 : JY9702Core.h
  • PFI_0_IN_1 : JY9702Core.h
  • PFI_0_IN_2 : JY9702Core.h
  • PFI_0_IN_3 : JY9702Core.h
  • PFI_0_IN_4 : JY9702Core.h
  • PFI_0_IN_5 : JY9702Core.h
  • PFI_0_IN_6 : JY9702Core.h
  • PFI_0_IN_7 : JY9702Core.h
  • PFI_0_OUT_0 : JY9702Core.h
  • PFI_0_OUT_1 : JY9702Core.h
  • PFI_0_OUT_2 : JY9702Core.h
  • PFI_0_OUT_3 : JY9702Core.h
  • PFI_0_OUT_4 : JY9702Core.h
  • PFI_0_OUT_5 : JY9702Core.h
  • PFI_0_OUT_6 : JY9702Core.h
  • PFI_0_OUT_7 : JY9702Core.h
  • PFI_In_0 : JY9702Core.h
  • PFI_In_1 : JY9702Core.h
  • PFI_In_2 : JY9702Core.h
  • PFI_In_3 : JY9702Core.h
  • PFI_In_4 : JY9702Core.h
  • PFI_In_5 : JY9702Core.h
  • PFI_In_6 : JY9702Core.h
  • PFI_In_7 : JY9702Core.h
  • PFI_Out_0 : JY9702Core.h
  • PFI_Out_1 : JY9702Core.h
  • PFI_Out_2 : JY9702Core.h
  • PFI_Out_3 : JY9702Core.h
  • PFI_Out_4 : JY9702Core.h
  • PFI_Out_5 : JY9702Core.h
  • PFI_Out_6 : JY9702Core.h
  • PFI_Out_7 : JY9702Core.h
  • PFI_PXI_Trig_IN_0 : JY9702Core.h
  • PFI_PXI_Trig_IN_1 : JY9702Core.h
  • PFI_PXI_Trig_IN_2 : JY9702Core.h
  • PFI_PXI_Trig_IN_3 : JY9702Core.h
  • PFI_PXI_Trig_IN_4 : JY9702Core.h
  • PFI_PXI_Trig_IN_5 : JY9702Core.h
  • PFI_PXI_Trig_IN_6 : JY9702Core.h
  • PFI_PXI_Trig_IN_7 : JY9702Core.h
  • PFI_PXI_Trig_OUT_0 : JY9702Core.h
  • PFI_PXI_Trig_OUT_1 : JY9702Core.h
  • PFI_PXI_Trig_OUT_2 : JY9702Core.h
  • PFI_PXI_Trig_OUT_3 : JY9702Core.h
  • PFI_PXI_Trig_OUT_4 : JY9702Core.h
  • PFI_PXI_Trig_OUT_5 : JY9702Core.h
  • PFI_PXI_Trig_OUT_6 : JY9702Core.h
  • PFI_PXI_Trig_OUT_7 : JY9702Core.h
  • PFI_Trigger_ui_0_0_di_OUT : JY9702Core.h
  • PFI_Trigger_ui_0_0_do_IN : JY9702Core.h
  • Pll_Sync : JY9702Core.h
  • pll_sync_IN : JY9702Core.h
  • Pll_Sync_Master_Trigger : JY9702Core.h
  • pll_sync_OUT : JY9702Core.h
  • Pll_Sync_Trigger_Valid : JY9702Core.h
  • Pll_Sync_Trigger_Valid_Not : JY9702Core.h
  • PllSyncModeHardware : JY9702Core.h
  • PllSyncModeSoftware : JY9702Core.h
  • PllWorkMode_Dual_Loop : JY9702Core.h
  • PllWorkMode_Dual_Loop_With_Nested_Zero_Delay : JY9702Core.h
  • PllWorkMode_PLL2_Single_Loop : JY9702Core.h
  • PXI_Trig_In_0 : JY9702Core.h
  • PXI_Trig_In_1 : JY9702Core.h
  • PXI_Trig_In_2 : JY9702Core.h
  • PXI_Trig_In_3 : JY9702Core.h
  • PXI_Trig_In_4 : JY9702Core.h
  • PXI_Trig_In_5 : JY9702Core.h
  • PXI_Trig_In_6 : JY9702Core.h
  • PXI_Trig_In_7 : JY9702Core.h
  • PXI_Trig_Out0 : JY9702Core.h
  • PXI_Trig_Out1 : JY9702Core.h
  • PXI_Trig_Out2 : JY9702Core.h
  • PXI_Trig_Out3 : JY9702Core.h
  • PXI_Trig_Out4 : JY9702Core.h
  • PXI_Trig_Out5 : JY9702Core.h
  • PXI_Trig_Out6 : JY9702Core.h
  • PXI_Trig_Out7 : JY9702Core.h

- r -

  • Rising_Edge_Trigger : JY9702Core.h
  • Routing_Matrix_0_p_0_2_out_IN : JY9702Core.h

- s -

  • SampleClk : JY9702Core.h
  • SampleClockSource_External : JY9702Core.h
  • SampleClockSource_Internal : JY9702Core.h
  • Sine : JY9702Core.h
  • SoftTrigger : JY9702Core.h
  • Square : JY9702Core.h
  • Standard_Waveform_0_sync_ch0_OUT : JY9702Core.h
  • Standard_Waveform_0_sync_ch1_OUT : JY9702Core.h
  • Standard_Waveform_sync_ch0 : JY9702Core.h
  • Standard_Waveform_sync_ch1 : JY9702Core.h
  • Stream : JY9702Core.h

- t -

  • Triangle : JY9702Core.h
  • TriggerIn : JY9702Core.h
  • TriggerOut : JY9702Core.h
  • Tx_Engine_0_generation_done_OUT : JY9702Core.h
  • Tx_Engine_0_ready_for_start_trigger_OUT : JY9702Core.h
  • Tx_Engine_0_running_OUT : JY9702Core.h
  • Tx_Engine_0_start_trigger_in_IN : JY9702Core.h
  • Tx_Engine_0_start_trigger_out_OUT : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- f -

  • Falling_Edge_Trigger : JY9702Core.h
  • Finite : JY9702Core.h


- j -

  • JY9702__DI_ReadSinglePoint_U8() : JY9702Core.h
  • JY9702_DI_AddLines() : JY9702Core.h
  • JY9702_DI_ReadSinglePoint() : JY9702Core.h
  • JY9702_DI_Start() : JY9702Core.h
  • JY9702_DI_Stop() : JY9702Core.h
  • JY9702_DO_AddLines() : JY9702Core.h
  • JY9702_DO_Start() : JY9702Core.h
  • JY9702_DO_Stop() : JY9702Core.h
  • JY9702_DO_WriteSinglePoint() : JY9702Core.h
  • JY9702_DO_WriteSinglePoint_U8() : JY9702Core.h
  • JY9702Core_AWG_CheckPllStatus() : JY9702Core.h
  • JY9702Core_AWG_Commit() : JY9702Core.h
  • JY9702Core_AWG_ConfigDDS() : JY9702Core.h
  • JY9702Core_AWG_ConfigMultiBoardSync() : JY9702Core.h
  • JY9702Core_AWG_ConfigPll() : JY9702Core.h
  • JY9702Core_AWG_GetChannelDelay() : JY9702Core.h
  • JY9702Core_AWG_GetGenerationStatus() : JY9702Core.h
  • JY9702Core_AWG_GetSampleRate() : JY9702Core.h
  • JY9702Core_AWG_HardwareSyncClkOutPost() : JY9702Core.h
  • JY9702Core_AWG_HardwareSyncClkOutPre() : JY9702Core.h
  • JY9702Core_AWG_Init() : JY9702Core.h
  • JY9702Core_AWG_SendSoftwareTrigger() : JY9702Core.h
  • JY9702Core_AWG_SetBasebandModeEnabled() : JY9702Core.h
  • JY9702Core_AWG_SetBufferLength() : JY9702Core.h
  • JY9702Core_AWG_SetCenterFrequency() : JY9702Core.h
  • JY9702Core_AWG_SetChannelDelay() : JY9702Core.h
  • JY9702Core_AWG_SetDataSource() : JY9702Core.h
  • JY9702Core_AWG_SetDigitalGain() : JY9702Core.h
  • JY9702Core_AWG_SetDigitalTrigger() : JY9702Core.h
  • JY9702Core_AWG_SetEnabledChannels() : JY9702Core.h
  • JY9702Core_AWG_SetEnableInterpolator() : JY9702Core.h
  • JY9702Core_AWG_SetEnableInverseSinc() : JY9702Core.h
  • JY9702Core_AWG_SetGenerationMode() : JY9702Core.h
  • JY9702Core_AWG_SetOutputRange() : JY9702Core.h
  • JY9702Core_AWG_SetSampleRate() : JY9702Core.h
  • JY9702Core_AWG_SetSamplesToWrite() : JY9702Core.h
  • JY9702Core_AWG_SetSlaveSamplaClkSyncTrigger() : JY9702Core.h
  • JY9702Core_AWG_SetSyncClkMode() : JY9702Core.h
  • JY9702Core_AWG_SetTriggerType() : JY9702Core.h
  • JY9702Core_AWG_Start() : JY9702Core.h
  • JY9702Core_AWG_Stop() : JY9702Core.h
  • JY9702Core_AWG_WriteDataBinary16() : JY9702Core.h
  • JY9702Core_AWG_WriteDbl64() : JY9702Core.h
  • JY9702Core_Close() : JY9702Core.h
  • JY9702Core_ConfigDeviceClock() : JY9702Core.h
  • JY9702Core_ExportSignal() : JY9702Core.h
  • JY9702Core_GetDeviceList() : JY9702Core.h
  • JY9702Core_GetLastError() : JY9702Core.h
  • JY9702Core_GetTemperature() : JY9702Core.h
  • JY9702Core_Open() : JY9702Core.h
  • JY9702Core_Open_WithAliasName() : JY9702Core.h
  • JY9702Core_ResetGPIO() : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- g -

  • GenerationMode : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- h -

  • Handle : JY9702Core.h
  • High_Level_Trigger : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- i -

  • ImmediateTrigger : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- j -

  • JY9702__DI_ReadSinglePoint_U8() : JY9702Core.h
  • JY9702_DeviceProperty : JY9702Core.h
  • JY9702_DI_AddLines() : JY9702Core.h
  • JY9702_DI_ReadSinglePoint() : JY9702Core.h
  • JY9702_DI_Start() : JY9702Core.h
  • JY9702_DI_Stop() : JY9702Core.h
  • JY9702_DO_AddLines() : JY9702Core.h
  • JY9702_DO_Start() : JY9702Core.h
  • JY9702_DO_Stop() : JY9702Core.h
  • JY9702_DO_WriteSinglePoint() : JY9702Core.h
  • JY9702_DO_WriteSinglePoint_U8() : JY9702Core.h
  • JY9702_Independent : JY9702Core.h
  • JY9702_MASTER : JY9702Core.h
  • JY9702_SLAVE : JY9702Core.h
  • JY9702Core_AWG_CheckPllStatus() : JY9702Core.h
  • JY9702Core_AWG_Commit() : JY9702Core.h
  • JY9702Core_AWG_ConfigDDS() : JY9702Core.h
  • JY9702Core_AWG_ConfigMultiBoardSync() : JY9702Core.h
  • JY9702Core_AWG_ConfigPll() : JY9702Core.h
  • JY9702Core_AWG_GetChannelDelay() : JY9702Core.h
  • JY9702Core_AWG_GetGenerationStatus() : JY9702Core.h
  • JY9702Core_AWG_GetSampleRate() : JY9702Core.h
  • JY9702Core_AWG_HardwareSyncClkOutPost() : JY9702Core.h
  • JY9702Core_AWG_HardwareSyncClkOutPre() : JY9702Core.h
  • JY9702Core_AWG_Init() : JY9702Core.h
  • JY9702Core_AWG_SendSoftwareTrigger() : JY9702Core.h
  • JY9702Core_AWG_SetBasebandModeEnabled() : JY9702Core.h
  • JY9702Core_AWG_SetBufferLength() : JY9702Core.h
  • JY9702Core_AWG_SetCenterFrequency() : JY9702Core.h
  • JY9702Core_AWG_SetChannelDelay() : JY9702Core.h
  • JY9702Core_AWG_SetDataSource() : JY9702Core.h
  • JY9702Core_AWG_SetDigitalGain() : JY9702Core.h
  • JY9702Core_AWG_SetDigitalTrigger() : JY9702Core.h
  • JY9702Core_AWG_SetEnabledChannels() : JY9702Core.h
  • JY9702Core_AWG_SetEnableInterpolator() : JY9702Core.h
  • JY9702Core_AWG_SetEnableInverseSinc() : JY9702Core.h
  • JY9702Core_AWG_SetGenerationMode() : JY9702Core.h
  • JY9702Core_AWG_SetOutputRange() : JY9702Core.h
  • JY9702Core_AWG_SetSampleRate() : JY9702Core.h
  • JY9702Core_AWG_SetSamplesToWrite() : JY9702Core.h
  • JY9702Core_AWG_SetSlaveSamplaClkSyncTrigger() : JY9702Core.h
  • JY9702Core_AWG_SetSyncClkMode() : JY9702Core.h
  • JY9702Core_AWG_SetTriggerType() : JY9702Core.h
  • JY9702Core_AWG_Start() : JY9702Core.h
  • JY9702Core_AWG_Stop() : JY9702Core.h
  • JY9702Core_AWG_WriteDataBinary16() : JY9702Core.h
  • JY9702Core_AWG_WriteDbl64() : JY9702Core.h
  • JY9702Core_Close() : JY9702Core.h
  • JY9702Core_ConfigDeviceClock() : JY9702Core.h
  • JY9702Core_ExportSignal() : JY9702Core.h
  • JY9702Core_GetDeviceList() : JY9702Core.h
  • JY9702Core_GetLastError() : JY9702Core.h
  • JY9702Core_GetTemperature() : JY9702Core.h
  • JY9702Core_Open() : JY9702Core.h
  • JY9702Core_Open_WithAliasName() : JY9702Core.h
  • JY9702Core_ResetGPIO() : JY9702Core.h
  • JYDLL_API : JY9702Core.h
  • JYFailed : JY9702Core.h
  • JYSuccess : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- l -

  • Lmk048xxCheckPllStatusCnt : JY9702Core.h
  • Low_Level_Trigger : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- n -

  • NoError : JY9702Core.h
  • None : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- p -

  • PFI_0_IN_0 : JY9702Core.h
  • PFI_0_IN_1 : JY9702Core.h
  • PFI_0_IN_2 : JY9702Core.h
  • PFI_0_IN_3 : JY9702Core.h
  • PFI_0_IN_4 : JY9702Core.h
  • PFI_0_IN_5 : JY9702Core.h
  • PFI_0_IN_6 : JY9702Core.h
  • PFI_0_IN_7 : JY9702Core.h
  • PFI_0_OUT_0 : JY9702Core.h
  • PFI_0_OUT_1 : JY9702Core.h
  • PFI_0_OUT_2 : JY9702Core.h
  • PFI_0_OUT_3 : JY9702Core.h
  • PFI_0_OUT_4 : JY9702Core.h
  • PFI_0_OUT_5 : JY9702Core.h
  • PFI_0_OUT_6 : JY9702Core.h
  • PFI_0_OUT_7 : JY9702Core.h
  • PFI_In_0 : JY9702Core.h
  • PFI_In_1 : JY9702Core.h
  • PFI_In_2 : JY9702Core.h
  • PFI_In_3 : JY9702Core.h
  • PFI_In_4 : JY9702Core.h
  • PFI_In_5 : JY9702Core.h
  • PFI_In_6 : JY9702Core.h
  • PFI_In_7 : JY9702Core.h
  • PFI_Out_0 : JY9702Core.h
  • PFI_Out_1 : JY9702Core.h
  • PFI_Out_2 : JY9702Core.h
  • PFI_Out_3 : JY9702Core.h
  • PFI_Out_4 : JY9702Core.h
  • PFI_Out_5 : JY9702Core.h
  • PFI_Out_6 : JY9702Core.h
  • PFI_Out_7 : JY9702Core.h
  • PFI_PXI_Trig_IN_0 : JY9702Core.h
  • PFI_PXI_Trig_IN_1 : JY9702Core.h
  • PFI_PXI_Trig_IN_2 : JY9702Core.h
  • PFI_PXI_Trig_IN_3 : JY9702Core.h
  • PFI_PXI_Trig_IN_4 : JY9702Core.h
  • PFI_PXI_Trig_IN_5 : JY9702Core.h
  • PFI_PXI_Trig_IN_6 : JY9702Core.h
  • PFI_PXI_Trig_IN_7 : JY9702Core.h
  • PFI_PXI_Trig_OUT_0 : JY9702Core.h
  • PFI_PXI_Trig_OUT_1 : JY9702Core.h
  • PFI_PXI_Trig_OUT_2 : JY9702Core.h
  • PFI_PXI_Trig_OUT_3 : JY9702Core.h
  • PFI_PXI_Trig_OUT_4 : JY9702Core.h
  • PFI_PXI_Trig_OUT_5 : JY9702Core.h
  • PFI_PXI_Trig_OUT_6 : JY9702Core.h
  • PFI_PXI_Trig_OUT_7 : JY9702Core.h
  • PFI_Trigger_ui_0_0_di_OUT : JY9702Core.h
  • PFI_Trigger_ui_0_0_do_IN : JY9702Core.h
  • Pll_Sync : JY9702Core.h
  • pll_sync_IN : JY9702Core.h
  • Pll_Sync_Master_Trigger : JY9702Core.h
  • pll_sync_OUT : JY9702Core.h
  • Pll_Sync_Trigger_Valid : JY9702Core.h
  • Pll_Sync_Trigger_Valid_Not : JY9702Core.h
  • PllSyncMode : JY9702Core.h
  • PllSyncModeHardware : JY9702Core.h
  • PllSyncModeSoftware : JY9702Core.h
  • PllWorkMode : JY9702Core.h
  • PllWorkMode_Dual_Loop : JY9702Core.h
  • PllWorkMode_Dual_Loop_With_Nested_Zero_Delay : JY9702Core.h
  • PllWorkMode_PLL2_Single_Loop : JY9702Core.h
  • PXI_Trig_In_0 : JY9702Core.h
  • PXI_Trig_In_1 : JY9702Core.h
  • PXI_Trig_In_2 : JY9702Core.h
  • PXI_Trig_In_3 : JY9702Core.h
  • PXI_Trig_In_4 : JY9702Core.h
  • PXI_Trig_In_5 : JY9702Core.h
  • PXI_Trig_In_6 : JY9702Core.h
  • PXI_Trig_In_7 : JY9702Core.h
  • PXI_Trig_Out0 : JY9702Core.h
  • PXI_Trig_Out1 : JY9702Core.h
  • PXI_Trig_Out2 : JY9702Core.h
  • PXI_Trig_Out3 : JY9702Core.h
  • PXI_Trig_Out4 : JY9702Core.h
  • PXI_Trig_Out5 : JY9702Core.h
  • PXI_Trig_Out6 : JY9702Core.h
  • PXI_Trig_Out7 : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- r -

  • RefClockSource : JY9702Core.h
  • Rising_Edge_Trigger : JY9702Core.h
  • Routing_Matrix_0_IN : JY9702Core.h
  • Routing_Matrix_0_OUT : JY9702Core.h
  • Routing_Matrix_0_p_0_2_out_IN : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- s -

  • SampleClk : JY9702Core.h
  • SampleClockSource : JY9702Core.h
  • SampleClockSource_External : JY9702Core.h
  • SampleClockSource_Internal : JY9702Core.h
  • Sine : JY9702Core.h
  • SoftTrigger : JY9702Core.h
  • Square : JY9702Core.h
  • Standard_Waveform_0_sync_ch0_OUT : JY9702Core.h
  • Standard_Waveform_0_sync_ch1_OUT : JY9702Core.h
  • Standard_Waveform_sync_ch0 : JY9702Core.h
  • Standard_Waveform_sync_ch1 : JY9702Core.h
  • StandardWaveformType : JY9702Core.h
  • STDCALL : JY9702Core.h
  • Stream : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- t -

  • Triangle : JY9702Core.h
  • TriggerIn : JY9702Core.h
  • TriggerOut : JY9702Core.h
  • Tx_Engine_0_generation_done_OUT : JY9702Core.h
  • Tx_Engine_0_ready_for_start_trigger_OUT : JY9702Core.h
  • Tx_Engine_0_running_OUT : JY9702Core.h
  • Tx_Engine_0_start_trigger_in_IN : JY9702Core.h
  • Tx_Engine_0_start_trigger_out_OUT : JY9702Core.h


  • BYTE : JY9702Core.h
  • Handle : JY9702Core.h
  • UINT64 : JY9702Core.h


Here is a list of all file members with links to the files they belong to:

- u -

  • UINT64 : JY9702Core.h


9702 C++ Programming Manual: Main Page

9702 C++ Programming Manual Documentation


9702 C++ Programming Manual: Member List

JY9702CoreCalibrationConstant Member List

This is the complete list of members for JY9702CoreCalibrationConstant, including all inherited members.

AWG_CH0_FS_mA_Range10Vpp | JY9702CoreCalibrationConstant
AWG_CH0_FS_mA_Range1Vpp | JY9702CoreCalibrationConstant
AWG_CH0_FS_mA_Range2p5Vpp | JY9702CoreCalibrationConstant
AWG_CH0_Offset_Range10Vpp | JY9702CoreCalibrationConstant
AWG_CH0_Offset_Range1Vpp | JY9702CoreCalibrationConstant
AWG_CH0_Offset_Range2p5Vpp | JY9702CoreCalibrationConstant
AWG_CH1_FS_mA_Range10Vpp | JY9702CoreCalibrationConstant
AWG_CH1_FS_mA_Range1Vpp | JY9702CoreCalibrationConstant
AWG_CH1_FS_mA_Range2p5Vpp | JY9702CoreCalibrationConstant
AWG_CH1_Offset_Range10Vpp | JY9702CoreCalibrationConstant
AWG_CH1_Offset_Range1Vpp | JY9702CoreCalibrationConstant
AWG_CH1_Offset_Range2p5Vpp | JY9702CoreCalibrationConstant


9702 C++ Programming Manual: Member List

JY9702CoreCalibrationInfo Member List

This is the complete list of members for JY9702CoreCalibrationInfo, including all inherited members.

CalibrationCRC16 | JY9702CoreCalibrationInfo
CalibrationDataAddress | JY9702CoreCalibrationInfo
CalibrationInfo | JY9702CoreCalibrationInfo
CalibrationSize | JY9702CoreCalibrationInfo
CalibrationTemperature | JY9702CoreCalibrationInfo
CalibrationTimeStamp | JY9702CoreCalibrationInfo
CurrentRegionSize | JY9702CoreCalibrationInfo
NextRegionAddress | JY9702CoreCalibrationInfo
PreRegionAddress | JY9702CoreCalibrationInfo
RegionType | JY9702CoreCalibrationInfo


9702 C++ Programming Manual: Member List

JY9702CoreDeviceInfo Member List

This is the complete list of members for JY9702CoreDeviceInfo, including all inherited members.

CalibrationAddr | JY9702CoreDeviceInfo
EEPROMSize | JY9702CoreDeviceInfo
HWRev | JY9702CoreDeviceInfo
Model | JY9702CoreDeviceInfo
ProductionDate | JY9702CoreDeviceInfo
Reserved | JY9702CoreDeviceInfo
SerialNumber | JY9702CoreDeviceInfo
StartSentinel | JY9702CoreDeviceInfo


9702 C++ Programming Manual: Member List

JY9702DeviceInfo Member List

This is the complete list of members for JY9702DeviceInfo, including all inherited members.

aliasName | JY9702DeviceInfo
DriverSetVer | JY9702DeviceInfo
FirmwareVer | JY9702DeviceInfo
FrameworkVer | JY9702DeviceInfo
HardwareVer | JY9702DeviceInfo
model | JY9702DeviceInfo
ProductionDate | JY9702DeviceInfo
serialNumber | JY9702DeviceInfo
slotNumber | JY9702DeviceInfo